9cce513645
jesd204/axi_jesd204_tx: Update version
2020-02-10 09:47:07 +02:00
b8e1daa22b
jesd204/axi_jesd204_rx: Update version
2020-02-10 09:47:07 +02:00
587a3c1a8d
scripts/jesd204.tcl: Added 64b mode to Rx scripting
2020-02-10 09:47:07 +02:00
72186324f3
tb/loopback_64b_tb: Testbench for 64b mode
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Data integrity check over a loopbacked link.
2020-02-10 09:47:07 +02:00
bd9836886f
jesd204_rx_static_config: Added 64b mode to Rx static config
2020-02-10 09:47:07 +02:00
c3afbbc8a8
jesd204/interfaces: Added 64b mode Rx signals
2020-02-10 09:47:07 +02:00
7cad1f81d9
axi_jesd204_rx: Added 64b mode
2020-02-10 09:47:07 +02:00
d1072847df
jesd204_rx: 64b mode support for receive peripheral
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Instantiate 64B/66B decoder based on synthesis parameter.
2020-02-10 09:47:07 +02:00
075f703443
jesd204_tx_static_config: Added 64b mode Tx static config
2020-02-10 09:47:07 +02:00
e2d12a5b53
jesd204/scripts: Add 64b mode to Tx scripting
2020-02-10 09:47:07 +02:00
c574861bf4
axi_jesd204_tx: Add 64b mode for control interface
2020-02-10 09:47:07 +02:00
d9a31e8d83
jesd204_tx: Support for 64b mode in transmit peripheral
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Instantiate 64B/66B mode encoder based on synthesis parameter.
2020-02-10 09:47:07 +02:00
b40e055ebe
jesd204/jesd204_common/jesd204_lmfc: Add multiblock clock edge, EoEMB
2020-02-10 09:47:07 +02:00
72e9a563da
jesd204_common: Added JESD204C components
2020-02-10 09:47:07 +02:00
20ae7a8f7d
jesd204: CRC12 component
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The component can be used in Tx to compute CRC on the data to be send as
in the Rx side to compute CRC on the received data.
2020-02-10 09:47:07 +02:00
a5346412d1
jesd204: Scrambler for 64b mode
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The component can be used for scrambling in Tx and descrambling on the
Rx side of the JESD link.
2020-02-10 09:47:07 +02:00
474e07e579
jesd204: Add parameter for TPL data width
2020-02-10 09:47:07 +02:00
f2060e27be
jesd204_tx: add output pipeline stage
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In order to help timing closure on multi SLR FPGAs add a pipeline stage
between the link layer and physical layer. This will add a fixed amount
of delay to the overall latency.
2020-02-07 09:02:46 +02:00
80a77b1e1b
ad_rst_constr: Added the quiet option
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critical warnings were caused by this file when the ad_rst.v instantiation
was done using generate depending on a parameter (i.e. axi_spi_engine)
2020-01-20 15:26:48 +02:00
18a8ef8ad5
axi_generic_adc: Added constraints to ip
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ad_rst.v module was missing the xdc
2020-01-17 16:46:31 +02:00
ca623e4845
axi_laser_driver: Fixed reorder issue in ip tcl
2020-01-13 12:25:23 +02:00
e6aa3a3b38
axi_ad9361: Fixed reorder issue in ip tcl
2020-01-13 12:25:23 +02:00
afb28280c2
axi_gpreg: added constraints for clock_mon module
2020-01-13 12:25:23 +02:00
9caaba54d3
ad_mem_asym: Force the Xilinx synthesizer to infer Block RAMs
2020-01-13 12:25:23 +02:00
53cb087b9c
ad_rst_constr: changed hier to hierarchical
2020-01-13 12:25:23 +02:00
f07652ab5a
axi_spi_engine: Add constraint for reset synchronizer
2020-01-13 12:25:23 +02:00
d2d7f2a3f9
up_clk_mon_constr: -heir is deprecated, use hierarchical instead
2020-01-13 12:25:23 +02:00
4511f731af
axi_laser_driver: Fix ip.tcl file
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- Add a missing contraint file
- Fix the path of the ttclk file
2020-01-13 12:25:23 +02:00
87a752e242
ad_rst_constr: Search pin in all hierarchy
2020-01-13 12:25:23 +02:00
adfeb435a4
scripts: Update Vivado version to 2019.1
2020-01-13 12:25:23 +02:00
25816ac1b3
adi_project_xilinx: removed set_property SCOPED_TO_REF
2020-01-13 12:25:23 +02:00
c684c2cbd6
scripts/adi_ip_xilinx.tcl: add variable width for multi bus interfaces
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Bus sizes often depend on parameters. In such cases the physical indexes
of the interfaces from the multi bus must be calculated based on parameters.
For each interface expose the formula that calculates the indexes to the
block design.
2020-01-13 09:55:25 +02:00
b93c1e6e90
intel/adi_jesd204: add bonded clock network support ( #408 )
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* jesd204b: add bonding clocks feature (fix for some routing issues)
* intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6
* intel/adi_jesd204: clock network option renamed according to intel documentation
* intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode
Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>
2020-01-09 17:45:32 +02:00
3235c9189c
axi_xcvrlb: added new parameters to IP
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added PLL locked reg to axi regmap; IP now recognizez xcvr type
automatically
2020-01-07 16:18:33 +02:00
9180d4dd39
library/axi_clkgen: Fix second clock output
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A typo prevents the usage of second clock output.
2020-01-07 13:21:00 +02:00
a25323b246
util_adcfifo: fix read pointer
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Read pointer should be always behind the write pointer except when it
reaches the last memory location where the writer stops.
2019-12-03 17:27:29 +02:00
e6d63ec50d
util_pack: Initital support for 32 channels
2019-11-28 16:17:58 +02:00
7612b5d8dd
scripts/jesd204.tcl: add support for more lanes and converters for TPLs
2019-11-28 16:17:21 +02:00
85eabc5a08
jesd204/ad_ip_jesd204_tpl_dac: add support for more lanes and converters
2019-11-28 16:17:21 +02:00
002f8d8a3e
jesd204/ad_ip_jesd204_tpl_adc: add support for more lanes and converters
2019-11-28 16:17:21 +02:00
db573a59b0
jesd204: support for 16 lanes
2019-11-28 16:17:21 +02:00
cd5848976e
axi_adc_trigger: Change out hold counter width
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Chance out hold_counter width form 17 to 20 bits.
Out hold period max ~ 20 ms. Default out hold period 2 ms.
2019-11-26 15:15:58 +00:00
4fdaa7fe12
axi_adc_trigger: Cosmetic change only
2019-11-26 15:15:58 +00:00
bdd44e37df
axi_adc_trigger: Dynamically set the out pin hold period
2019-11-26 15:15:58 +00:00
4c2a539a96
axi_fan_control: Fixed ip version
2019-11-26 13:33:41 +02:00
e0813d49b6
axi_adc_trigger: Fix two sample offset
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When using a non-maximum sampling rate the data is captured earlier by two
samples.
After the initial trigger jitter fix, a low latency/utilization was
desired(one sample delay for the trigger detection). After adding the
instrument trigger an equal latency between ADC and LA was required, hence the
need for a two sample delay on the trigger path. The delay was implemented
as two clock cycle delays not two sample delays.
This commit fixes this issue and offers a more robust design.
2019-11-25 13:14:18 +00:00
d844167850
axi_adc_trigger: Fix trigger jitter
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A trigger jitter was added by fix on the external trigger input. It
manifests at input sampling frequencies lower than the maximum frequency.
Added the required reset and CE(valid) signal to the last output
stages of the trigger to obtain the desired functionality for all
sampling rates.
2019-11-25 13:14:18 +00:00
ecfa6bd19d
axi_logic_analyzer: Add holdoff support
2019-11-25 13:14:18 +00:00
ede19a3b3d
axi_adc_trigger: Add holdoff support
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Add reset pin for holdoff.
2019-11-25 13:14:18 +00:00
24b5de4438
sysid: Specified clock interface for input clk
2019-11-20 10:43:54 +02:00
Laszlo Nagy
Arpadi
Istvan Csomortani
cycollineau
AndreiGrozav