ddc7c845e9
fmcomms2_udc: Initial check in
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FMCOMMS2 with an additional SPI port for the up/down converter board
2014-10-09 19:01:22 +03:00
6f77af4aff
fmcjesdadc1: Upgrade project to 2014.2
2014-10-09 18:55:27 +03:00
2da395926e
fmcomms2: Upgrade project to 2014.2
2014-10-09 18:54:33 +03:00
4f6aa159b8
mitx045: Base design now support 2014.2
2014-10-09 15:11:28 +03:00
edeeafa47d
ad9671_fmc: Added sof information to the AD9671 driver
2014-10-09 14:52:25 +03:00
072e11c661
ad9467_fmc: Upgrade the axi_quad_spi core
2014-10-08 15:22:58 +03:00
94e9396557
AD9467: Fixup swapped net names
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Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-10-08 10:45:32 +02:00
fc38249150
ad9467 ZED: Fix over range signal path, and the dma interface.
2014-10-08 11:24:44 +03:00
15db557bd6
ad9467 ZED: Cosmetic changes on bd script.
2014-10-08 11:24:32 +03:00
5565cf8fad
axi_ad9467: Independent read/write update
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Independent read/write operation is supported on "up" interface
2014-10-08 11:23:44 +03:00
82717b354a
ad9467_fmc : Upgrade project to 2014.2
2014-10-08 11:21:43 +03:00
b2d0260130
ad9467_fmc: Prevent to use concatenation module on SPI interface
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This module cause unnecessary issues during version upgrades.
2014-10-08 11:20:45 +03:00
88a3b7f8fd
library: remove all constraints for now
2014-10-07 16:59:19 -04:00
27153fff41
ad9625x2_fmc: updated to 2014.2
2014-10-07 16:05:09 -04:00
2dfcb0c599
usdrx1: Initial commit for a5gt
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axi_ad9671: added start of frame information to the altera core.
2014-10-07 19:41:54 +03:00
95842b8949
ad9434_fmc: Fix adc_valid signal path
2014-10-07 18:02:33 +03:00
a436153a48
axi_ad9434: Independent read/write update
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Independent read/write is supported on "up" interface.
2014-10-07 18:01:44 +03:00
115f33b8d6
ad9434_fmc: Fix pin constraints for ZC706
2014-10-07 17:58:29 +03:00
9404e93126
ad9434_fmc: Fix PN monitor.
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No need to flop the incoming data.
2014-10-07 17:56:27 +03:00
c1213ffe71
ad9434_fmc: Fix SPI interface
2014-10-07 17:51:14 +03:00
66baf6ac3e
axi_ad9434: Deleted unused ip file
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ad_lvds_in.v is not used in this ip core.
2014-10-07 17:47:08 +03:00
bfa17844ff
ad_serdes_in: General update
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Added a parameter for option SDR / DDR mode, added a parameter for parallel data width.
Note: default IF_TYPE is SDR and default PARALLEL_WIDTH is 8
2014-10-07 17:42:27 +03:00
151781a2af
axi_ad9467: Fix PN sequence checker
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Make sure that the reference PN sequence is only incremented every two clock
cycles to make sure that it matches the rate of the ADC PN sequence.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-07 16:26:53 +03:00
59640f181b
ad9467: Fix LVDS delay interface.
2014-10-07 16:25:22 +03:00
af618073a6
projects/common/xxx/xxx_system_bd.tcl: 'Update microblaze defaults
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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-07 09:18:47 +02:00
cd42345324
projects/common/xxx/xxx_system_bd.tcl: 'Update microblaze defaults
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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-07 09:17:24 +02:00
bca8ec0160
daq2: 2014.2 and ver.d
2014-10-06 14:56:01 -04:00
c375b5b26e
daq3: vivado build
2014-10-06 10:34:02 -04:00
d47776a4a0
ad9152: 9144 copy
2014-10-06 10:34:01 -04:00
525373fc04
daq3: daq2 copy
2014-10-06 10:34:00 -04:00
0539bc36c8
axi_ad9467: Fix PN sequence checker
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Make sure that the reference PN sequence is only incremented every two clock
cycles to make sure that it matches the rate of the ADC PN sequence.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-06 16:19:01 +02:00
b029d07adf
common: Connect audio clkgen reset
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While we are at it also hide the unused locked pin.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-06 16:17:33 +02:00
54053e0d87
common: Set cpu interconnect strategy to minimize area
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There will rarely be concurrent access to the peripheral control bus
interconnect, so there is no need to optimize for performace. Setting the
interconnect strategy to minimize area can reduce the resource usage by
~90%.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-06 16:17:33 +02:00
1defad36b8
fmcomms1: Connect DMA controller directly to the HP ports
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The AXI DMAC controller nativly supports AXI3, there is no need to insert a interconnect to do protocol conversion.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-06 16:17:33 +02:00
210da4116f
scripts: initial commit
2014-10-03 16:13:34 -04:00
581892b22a
axi_ad9265: Updated project with new up independent read/write
2014-10-03 12:32:08 +03:00
de33722470
up/constr: independent read/write and local constraints
2014-10-02 14:35:59 -04:00
801f12f373
ad9467: Fix LVDS delay interface.
2014-10-02 11:34:37 +03:00
f0927afd0b
ad9625_fmc: add dma fifo for non-zynq
2014-10-01 14:51:14 -04:00
68c0c72e53
util_dac_unpack: Fix unpack order with 1 channel
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Due to the delay between the dac_valid and the fifo_valid signal we need to
have two counters. One counter which counts the number of incoming
dac_valid signals and generates the dma_rd signal and one counter for the
offset which gets set to 0 when fifo_valid is set.
This fixes issues with the unpack order when only one channel is active.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-30 18:48:04 +02:00
98dd47e783
axi_spdif: Add missing signals to the regmap read sensitifity list
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-30 13:18:51 +02:00
f60e112b50
axi_spdif: Don't use non-static expressions in port assignments
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Fixes a warning from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-30 13:18:51 +02:00
8a994db28b
axi_spdif: Set unused signals to 0
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Fixes warnings about undriven signals from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-30 13:18:51 +02:00
96339ba96f
axi_i2s: Add missing signals to the regmap read process sensitivity list
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-30 13:18:51 +02:00
32dd1d1a4a
axi_i2s: Set unused signals to 0
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Fixes warnings from the tools about undriven signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-30 13:18:50 +02:00
e5a9633f84
axi_dmac: Add default driver values for optional input ports
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This silences warnings from the tools about undriven ports.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-30 13:18:50 +02:00
9e7eb81b76
axi_dmac: Hide fifo_wr_sync signal if C_SYNC_TRANSFER_START != 1
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The fifo_wr_sync signal is only used when C_SYNC_TRANSFER_START = 1, so hide it otherwise.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-30 13:18:50 +02:00
77cbf26241
axi_dmac: Hide fifo_wr bus when source type is not the fifo interface
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-30 13:18:50 +02:00
ff2e102182
axi_dmac: Add clock signal spec for m_axis/s_axis bus
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This silences warnings from the tools about having no clock assigned to the bus.
Also fix the name of the TVALID signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-30 13:18:50 +02:00
fd6b3b5427
fmcomms2: Connect DMA directly to the HP ports
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The DMA controller is able to send AXI3 compatible requests, no need to add
a interconnect for protocol conversion in between the DMA controller and the
HP port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-30 13:18:50 +02:00
Istvan Csomortani
Adrian Costina
Paul Cercueil
Rejeesh Kutty
Lars-Peter Clausen
Michael Hennerich