9bef9742b7
jesd_gt- cosmetic changes
2015-09-03 16:16:24 -04:00
84ced344d9
gtlb- up-sync make w1c
2015-09-03 16:16:22 -04:00
e0b5044aa3
axi_dmac: Disable dummy AXI ports for Xilinx IPI
...
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.
The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
2a09257f38
pzslb- updates - wip
2015-08-31 15:41:28 -04:00
c1b01517f8
util_gtlb: added
2015-08-31 15:41:22 -04:00
1e5afdd535
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
6cf7eb5ad4
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
4554eb03b0
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
704385a8dc
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
a33c08725b
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
1cd3435147
up_delay_cntrl- cosmetics
2015-08-28 13:16:18 -04:00
8fddf983d2
up_hdmi_tx- common/generic instance names
2015-08-27 13:17:06 -04:00
88f806f584
ad9361- alt io matching
2015-08-27 11:55:24 -04:00
74e72021f7
ad9361- ensm through dev-if
2015-08-27 11:41:53 -04:00
664ef017bb
ad9361- ensm through dev-if
2015-08-27 11:41:52 -04:00
29b0ec0378
ad9361- ensm through dev-if
2015-08-27 11:41:51 -04:00
d82d37c23f
ad9361- ensm through dev-if
2015-08-27 11:41:49 -04:00
2259b6cbf7
ad9361- ensm through dev-if
2015-08-27 11:41:48 -04:00
20ee10ea46
common/ad_lvds_out- add single ended
2015-08-27 11:41:47 -04:00
c56b534ec0
dacfifo- remove interfaces
2015-08-27 11:18:00 -04:00
ba64de228e
ip-constr- register name changes
2015-08-27 11:18:00 -04:00
f3410a7db1
xpack- remove useless interfaces
2015-08-26 14:12:14 -04:00
b0d22d323a
ad9361- axi-clock definitions
2015-08-26 14:11:43 -04:00
4655af7bf6
2015.2 updates
2015-08-26 11:33:44 -04:00
18f688514b
2015.2 updates
2015-08-26 11:33:37 -04:00
7780b3a3a2
2015.2 updates
2015-08-26 11:33:27 -04:00
7b858bc5ad
Revert commit 6b99ce
...
Revert 6b99ce2482
2015-08-26 13:48:28 +03:00
386cc74ab4
util_axis_fifo: Fix port names at util_axis_fifo_ip.tcl
...
Fix port names at the 'port_maps' attribute of the adi_add_bus process call.
2015-08-25 09:41:34 +03:00
c2ea667a01
library/IPI: Set ASSOCIATED_RESET parameter for AXI interface
...
For some reason, if a core has an AXI and an AXI Stream interface too, the tool sets the AXI interface's ASSOCIATED_RESET parameter to the AXI Stream interface's reset.
This cause an unconnected AXI reset port in the block design. This 'set_property' command intended to overwrite this automated setup.
2015-08-25 09:36:42 +03:00
0c3f110bff
library: Fix broken parameters
...
Fix the broken parameters for the following IP cores: axi_i2s_adi, axi_spdif_tx, util_cpack. Make additional name changes on the local parameters.
2015-08-25 09:19:47 +03:00
da315eb6c0
library: 2015.2 updates
...
IPI bus interface names have changed in this new release.
2015-08-25 09:13:24 +03:00
0077117f94
dac/adc- make common instances
2015-08-21 14:41:39 -04:00
c45d39df51
dac/adc- make common instances
2015-08-21 14:41:35 -04:00
e3ec6b48fc
dac/adc- make common instances
2015-08-21 14:41:30 -04:00
f31c1c9caa
dac/adc- make common instances
2015-08-21 14:41:26 -04:00
e4e4700950
dac/adc- make common instances
2015-08-21 14:41:13 -04:00
54b4365f6c
dac/adc- make common instances
2015-08-21 14:41:09 -04:00
799001403f
mult-macro: use primitive parameters
2015-08-20 13:54:16 -04:00
111287604b
xcvr- remove status constraint
2015-08-20 13:54:15 -04:00
0d482e7ef6
axi_dmac: Disable dummy AXI ports for Xilinx IPI
...
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.
The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-08-20 18:25:01 +02:00
d59ec3b36d
unused ip cores
2015-08-20 11:37:16 -04:00
b0079e60bf
ad-rst - common instance for adc/dac
2015-08-20 11:37:16 -04:00
d67a4a3088
axi_ad9434: Removed duplicate parameter
2015-08-20 18:19:59 +03:00
6b99ce2482
library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2
2015-08-20 18:17:38 +03:00
6ae0c8f85e
library: Fixed changes related to parameters
2015-08-20 18:13:54 +03:00
0d1d8310fd
axi_dmac: Parameter changes
...
Update parameters on inc_id.h and axi_dmac_ip.tcl
2015-08-20 16:06:26 +03:00
82e703df23
parameter changes
2015-08-20 08:53:51 -04:00
db18924f8a
library/scripts: Fix ipx::get_file_groups process call
...
ipx::get_file_groups does not work, if there is specified just a [<pattern>] for its argument. Need to use a -filter to get proper result.
2015-08-20 10:56:37 +03:00
0dfb3e2019
tcl_scripts: Update Vivado version number to 2015.2.1
2015-08-20 10:50:52 +03:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
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Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
Rejeesh Kutty
Lars-Peter Clausen
Istvan Csomortani
Adrian Costina