Commit Graph

2454 Commits (9b2a106aa0cf0b80ee3fb589fcc40d693015f6f9)

Author SHA1 Message Date
AndreiGrozav 9b2a106aa0 axi_jesd_gt: changed clock and reset naming to be consistent with the other projects 2016-03-15 11:20:31 +02:00
AndreiGrozav 06b7916303 axi_spdif_tx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred 2016-03-15 10:18:25 +02:00
AndreiGrozav ef05642e26 axi_spdif_rx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred 2016-03-15 10:14:05 +02:00
AndreiGrozav b3ed38107c axi_i2s_adi: changed adi_ip_properties lite to adi_ip_properties, so that the axi interface can be inferred 2016-03-15 10:12:45 +02:00
AndreiGrozav 31cc91d1b9 adi_ip: Updated to 2014.4.2
- automatically infer clocks, resets, axim_mm and axis interfaces
2016-03-14 15:14:18 +02:00
Adrian Costina 2524f19ae0 Updated interfaces Makefile and Makefiles for the libraries that depend on it 2016-03-07 12:31:41 +02:00
Adrian Costina 40fb68dfd5 ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible 2016-03-02 13:39:37 +02:00
Adrian Costina becc23a69b daq2: Modified common spi module so that spi streaming is possible
- stop incrementing spi_count after the instruction cycle
2016-03-01 17:25:58 +02:00
Rejeesh Kutty f6e64e42b0 kcu105: add ethernet idelaycntrl 2016-02-26 13:19:49 -05:00
Adrian Costina 8ccd8d87bb daq2: A10GX, increase analog/digital reset durations
- reset the xcvr_rst_cntrl only from the axi_jesd_xcvr
- checked separate RX/TX reset per channel
2016-02-23 11:41:38 +02:00
Adrian Costina 89f7aadfb1 fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output
This will allow for the transceivers to be reset by the axi_jesd_xcvr core
2016-02-23 11:31:07 +02:00
Adrian Costina 0f37dd6424 fmcjesdadc1: Fixed project
- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
Adrian Costina d94f157454 arradio: Changed ADC/DAC DMA address length to 24 bit 2016-02-16 15:27:51 +02:00
Adrian Costina 43e03ca6f7 arradio: Updated project
- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
2016-02-16 14:50:23 +02:00
Adrian Costina 61f9f72a75 fmcjesdadc1: Updated VC707 project for maximum throughput from DMA to DDR
- Increased the DMAs internal FIFO
2016-02-09 12:30:56 +02:00
Adrian Costina c431adb793 fmcjesdadc1: Updated KC705 project for maximum throughput from DMA to DDR
- Increased the DMA internal FIFO
2016-02-09 12:00:27 +02:00
Adrian Costina ad9ecbbbb6 daq2: Updated a10gx project to quartus 15.1.1 2016-02-05 17:43:05 +02:00
Adrian Costina 0d67af370f util_upack: Fixed problem when dac valid isn't continuous from the DAC
In cases when the dac_valid_ from the DAC is not continuous, in some situations
there were two dac_valid pulses sent to the DMA.
2016-02-04 13:03:46 +02:00
Istvan Csomortani e22d5d5c18 daq2: Fix clock constraints for KC705 and VC707 2016-01-22 19:09:57 +02:00
Adrian Costina 59fbd99fdb fmcjesdadc1: Added clock constraint for the ADC path 2016-01-22 15:46:20 +02:00
Adrian Costina dca39c26f9 ad6676evb: Added clock constraint for the ADC path 2016-01-22 15:45:16 +02:00
Adrian Costina 9cd0378003 fmcadc2: Added clock constraint for the ADC path 2016-01-22 15:44:04 +02:00
Adrian Costina 7013b319b0 motcon2_fmc: Fixed reset connection for cpack cores 2015-12-22 12:03:34 +02:00
Adrian Costina 34b832e22a fmcomms6: Fixed reset connection for cpack core 2015-12-16 10:36:33 +02:00
Adrian Costina 35f6bd16e9 fmcomms5: Fixed reset connection for cpack core 2015-12-16 10:34:36 +02:00
Adrian Costina 6e549171f0 fmcomms5: Connected the clk input of the ad9361 to l_clk 2015-12-02 14:43:44 +02:00
Adrian Costina 2309c4d83c Makefiles: Removed " from path 2015-11-27 14:02:46 +02:00
Adrian Costina 159f6c1216 Makefiles: Updated Makefiles
- for altera projects, taken into consideration of the new location for common qsys files
- for fmcomms5, added wfifo dependency
- for daq3, added mfifo dependency
2015-11-27 12:39:42 +02:00
Istvan Csomortani 36febf8591 Merge branch 'master' into dev
Conflicts:
	library/axi_ad9361/axi_ad9361_ip.tcl
	library/axi_dmac/Makefile
	library/axi_dmac/axi_dmac_constr.ttcl
	library/axi_dmac/axi_dmac_ip.tcl
	library/common/ad_tdd_control.v
	projects/daq2/common/daq2_bd.tcl
	projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
	projects/fmcomms2/zc706pr/system_project.tcl
	projects/fmcomms2/zc706pr/system_top.v
	projects/usdrx1/common/usdrx1_bd.tcl

This merge was made, to recover any forgotten fixes from master,
before creating the new release branch. All conflicts were reviewed
and resolved.
2015-11-26 13:38:11 +02:00
Adrian Costina 667e49fe41 library: Axi_clkgen, added register for controlling the source clock.
Address is 0x11 /0x44.
With the default value, 0, clock 1 is selected. If set to 1, clock 2 is selected
2015-11-25 11:16:32 +02:00
Adrian Costina ea57b3c03c daq2: A10GX, add project specific IP search paths 2015-11-25 10:58:36 +02:00
Adrian Costina df58646925 util_adcfifo: Updated altera interface 2015-11-25 10:20:06 +02:00
Adrian Costina e8a595b81e fmcjesdadc1: Updated a5soc design 2015-11-24 15:39:52 +02:00
Adrian Costina fd3910a915 fmcjesdadc1: Updated a5gt design 2015-11-24 15:39:21 +02:00
Adrian Costina 9281eb2c33 fmcjesdadc1: Updated common altera design 2015-11-24 15:38:58 +02:00
Istvan Csomortani 593c486168 ad_tdd_control: The state machine goes from OFF to ON, when a valid sync is received 2015-11-24 15:15:53 +02:00
Istvan Csomortani c70be7391f ad_tdd_control: Avoid unnecessary reset on control lines
No need to reset for tdd_last_burst, it's value depends on the tdd_burst_counter.
2015-11-24 15:13:18 +02:00
Adrian Costina a81625e1fa daq2: Updated a10gx project 2015-11-24 13:28:53 +02:00
Adrian Costina 605a0768e0 arradio: Updated c5soc project 2015-11-24 13:27:44 +02:00
Adrian Costina a0e67aad56 c5soc: Updated common design 2015-11-24 13:22:01 +02:00
Adrian Costina ee0617661e axi_ad9680: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:45:12 +02:00
Adrian Costina f51871c1e4 axi_ad9144: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:44:07 +02:00
Adrian Costina 76823f95fa axi_ad9250: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:39:55 +02:00
Adrian Costina 275ec3d3a8 axi_ad9361: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:21:08 +02:00
Adrian Costina 250f3c917b axi_ad9361: Removed old signals from the altera device interface module 2015-11-24 11:20:35 +02:00
Adrian Costina fb269f7a29 util_cpack: Updated altera interfaces
- DMA side, simplified naming
- ADC side, added FIFO conduit per channel
2015-11-24 11:18:18 +02:00
Adrian Costina e6de2ade78 util_upack: Updated altera interfaces
- DMA side, simplified naming
- DAC side, added FIFO conduit per channel
2015-11-24 11:17:02 +02:00
Adrian Costina c5ff1674c6 axi_dmac: Updated fifo interfaces for easier connectivity 2015-11-24 11:08:28 +02:00
Adrian Costina e5d2f5be06 util_upack: Cosmetic changes 2015-11-24 10:55:10 +02:00
Adrian Costina 985f2ca020 library: ad_rst, added comment so that the registers are not minimized away 2015-11-24 10:33:38 +02:00