Vivado recognises .h files as C header files,
the expected extension for Verilog Header is .vh
This causes issues in simulating block designs since these files
won't be exported for the simulation even if they are
part of the simulation fileset.
Allow to specify additional properties when defining a IP parameter. The
properties take the form of a list of key value pairs. E.g.
ad_ip_parameter ... { \
DISPLAY_NAME "Name" \
DISPLAY_HINT "radio" \
}
This helps to reduce the amount of boilerplate when additional properties
need to be specified for a parameter.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
TCL files can be helpful to automate certain tasks like creating timing
constraints. Add handling for them to the ad_ip_addfile function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The address width of the AXI interface depends on the size of the register
and can differ from peripheral to peripheral. Add a parameter to the
function that allows to specify the address width, this allows to use the
function for more peripherals.
Keep the current value of 16 bits as the default if the parameter is not
specified.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a tcl process, which can be used to generate custom module
names during the generation phase. This will be used to create
different ad_serdes_clk module, in case when independent IOPLLs are
needed for TX and RX.
Laszlo Nagy
Lars-Peter Clausen
Rejeesh Kutty
Istvan Csomortani