5edf61c40a
ad_rst:- allow preset to be synchronized as reset
2015-08-13 13:03:51 -04:00
2bcac36e33
common/up_- change to asynchronous resets
2015-08-13 13:03:51 -04:00
10d4da64dd
axi_jesd_gt: move master/slave control to a util module
2015-08-13 13:03:51 -04:00
e4f94664a6
axi_jesd_gt- remove per lane control/status to channel
2015-08-13 13:03:51 -04:00
f807490ed1
axi_jesd_gt- per lane group
2015-08-13 13:03:51 -04:00
4c8206608c
axi_jesd_gt- separate es-axi
2015-08-13 13:03:51 -04:00
e4b0710923
axi_jesd_gt- per lane split-up
2015-08-13 13:03:51 -04:00
ad80561379
TDD_regmap: Fix CDC for control signals
2015-08-06 15:16:39 +03:00
e19d476b58
TDD_regmap: Fix addresses
2015-08-06 15:15:50 +03:00
d2c99acae8
fmcomms2/TDD: Update synchronization interface
...
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
8e631e56d6
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
cd5ce3349f
iqcor- move i/q sel inside the module
2015-07-23 15:55:45 -04:00
a4461545fa
axi-ip: constraints - altera
2015-07-22 12:46:06 -04:00
559893c0a3
altera- obsolete cores
2015-07-21 11:04:26 -04:00
86dabbe5fc
jesd-align-- xilinx/altera merge
2015-07-21 10:57:00 -04:00
9f7fff2d2f
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
...
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 14:10:49 +03:00
6e3817d419
axi_jesd_xcvr: individual reset control
2015-07-13 10:04:34 -04:00
b25b2e3020
registers for signal tap
2015-07-08 15:47:45 -04:00
ea2bd71904
synchronize up signals separately
2015-07-07 12:51:13 -04:00
c1fcbeec8e
library/axi_jesd_xcvr: interface name matching
2015-07-07 10:21:53 -04:00
3a5da47239
xcvr- initial checkin
2015-07-06 13:51:55 -04:00
cf6052e2a8
axi_hdmi_tx: Add control to bypass chroma sub-sampler
...
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
d6c64e031f
axi_hdmi_rx: Drop TPG enable from register map
...
The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
542d64bb5a
up_hdmi_rx: Fix enable control
...
Connect the enable signal in the register map to the up_preset signal so
that it is possible to enable/disable to core at runtime.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
231a21548c
up_hdmi_rx: Fix TPM OOS clear
...
The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
185e489802
cpack- signaltap mess
2015-06-29 16:31:53 -04:00
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
ac6e28c461
library/common: add altera signaltap
2015-06-19 14:33:01 -04:00
ddc08c960c
ad_tdd_control: Connect the reset to all the flops
2015-06-11 12:07:47 +03:00
e2f4a4c5cf
library: make preset registered for timing paths
2015-06-10 13:41:41 -04:00
c926daca3a
ad9361/tdd: Fix generation of tx_valid_* signals
...
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:22:21 +03:00
2e877389b2
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 18:09:49 +03:00
3b1ea7e528
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
...
598ece4c8d
2015-06-04 18:09:47 +03:00
6548bcd71f
axi_ip- constraints: add rst path
2015-06-04 10:53:13 -04:00
e7470036bf
library- drp moved to up clock
2015-06-01 13:39:26 -04:00
aa24c442f5
a10gx- no-ddr
2015-06-01 11:00:01 -04:00
92fc0e050d
altera- common sdc
2015-06-01 10:59:57 -04:00
83df53d9bf
adc_common: Updated version because the delay registers have been changed
2015-05-25 17:18:14 +03:00
1ef83bd88b
axi_ad9671: Updated port names. Fixed synchronization of the rx_sof with the ad_jesd_align module, so that data valid is assigned correctly
2015-05-23 00:16:27 +03:00
660c84e01c
axi_ad9434 : Update the IO delay interface
2015-05-22 19:47:09 +03:00
0c6ef203c0
iobuf: do is a system-verilog keyword
2015-05-21 14:06:13 -04:00
9762c65868
library- jesd-align port name change
2015-05-20 14:25:21 -04:00
6e047f78c6
delay-cntrl: up-clk, direct access + tx
2015-05-18 14:28:20 -04:00
a07d11c3e9
axi_ad9361_tdd: Define control bits for continuous receive/transmit
2015-05-14 17:21:32 +03:00
7c9bc40c75
axi_ad9361&TDD: Update TDD
...
+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
2015-05-13 14:03:01 +03:00
2e7135c3c2
axi_ad9361_tdd: Initial commit.
...
Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 12:20:44 +03:00
d623f77453
axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst.
...
Resets for both up clock domain and rx clock domain are needed in some projects
2015-04-30 12:07:36 +03:00
a7a2d194e9
axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core
2015-04-28 15:04:18 +03:00
7c97e192f2
dma_fifo: Simplify FIFO WE condition
...
The only time we must not write to the FIFO is when it is full as this will
overwrite the first sample. Under all other conditions it is ok to write
data. If that data is invalid it will be overwritten when valid arrives.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:22 +02:00
b14721b8ae
library: Use common prefix for CDC signal names
...
Use a common naming scheme for CDC signals to make it easier to create
constraints for them.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:22 +02:00
e116822059
imageon_zc706: Updates and fixes
...
+ sync the sof to the dma_de signal
+ hdmi_rx_dma is connected to the HP1
+ fix syncronization signal in the CSC module
+ hdmi_rx_clk is asynchronous
2015-03-27 18:57:32 +02:00
552d9b41f7
imageon: updates
2015-03-24 15:08:48 -04:00
b29e97f985
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
80c2a5a45d
axi_hdmi_rx: General clean up
2015-03-23 12:39:26 +02:00
8dfcbdfd48
gt_channel/gt_common: simulation parameter warning fix
2015-03-06 12:36:07 -05:00
57e1f0e334
gt_channel/gt_common: simulation parameter warning fix
2015-03-06 12:36:03 -05:00
2d01955042
up_gt: change version dfe/lpm support
2015-03-05 09:47:16 -05:00
1613f7fb41
cftl_cip: Add util_pmod_fmeter IP to library
...
Frequency meter IP for CN0332.
2015-02-23 17:20:12 +02:00
2442b6e929
gt- report device type
2015-02-17 11:43:50 -05:00
de043ce130
gt_channel: lpm/dfe programmable
2015-02-13 11:33:04 -05:00
870ebdb562
up_gt: support lpm mode
2015-02-12 16:21:11 -05:00
1e7c9a3924
gt_es: support lpm mode - 2/2
2015-02-12 16:20:43 -05:00
0a8e6f62ef
gt_es: support lpm mode - 1/2
2015-02-12 15:15:18 -05:00
9e2e2ef44e
xfer-logic: stretch toggles to allow capture
2015-02-06 22:15:16 -05:00
e9231c8f36
xfer-logic: stretch toggles to allow capture
2015-02-06 22:15:14 -05:00
9f485f2f4e
common: Add register map module for HDMI receiver.
2015-01-08 12:24:47 +02:00
161e6cc70d
common: Add color space sampling and color space conversion modules
...
This two module are used by the HDMI receiver.
2015-01-08 12:24:46 +02:00
3a4d765a2b
up_clkgen: reading typo
2015-01-07 14:02:39 -05:00
1d6ea64d04
up_gt: move status to up clock
2014-12-16 08:48:13 -05:00
04c10abc2f
gth/gtx: share same cpll/qpll cpu settings
2014-12-11 11:18:48 -05:00
8cc9adfc49
up_axi: Fix up_raddr/up_waddr port width
...
Make sure that the port declaration width matches with the reg declaration
later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:22:28 +01:00
a4724f8396
es: added kcu105 gth
2014-11-17 09:55:12 -05:00
b1c91fac92
es: added kcu105 gth
2014-11-17 09:55:10 -05:00
c6df568a00
Revert "ad_interrupts: Initial check in."
...
This reverts commit b254380338
2014-11-06 12:16:52 +02:00
74ec396b27
ad_rst: ultrascale -dual stage
2014-11-05 16:47:41 -05:00
17cb1d9585
common/mem: asymmetric version
2014-10-30 11:12:09 -04:00
b254380338
ad_interrupts: Initial check in.
...
Initial check in of the interrupt concatenation block.
2014-10-27 19:34:34 +02:00
7e52cf9568
up_axi: timeout generating multiple/repeated acks
2014-10-23 13:51:33 -04:00
1d26639d73
common: Added synchronization mechanism to the up_adc_common module
2014-10-22 10:05:55 +03:00
2817ccdb22
up_axi: altera can not handle same clock assertion of arready and rvalid
2014-10-09 15:25:05 -04:00
2dfcb0c599
usdrx1: Initial commit for a5gt
...
axi_ad9671: added start of frame information to the altera core.
2014-10-07 19:41:54 +03:00
bfa17844ff
ad_serdes_in: General update
...
Added a parameter for option SDR / DDR mode, added a parameter for parallel data width.
Note: default IF_TYPE is SDR and default PARALLEL_WIDTH is 8
2014-10-07 17:42:27 +03:00
de33722470
up/constr: independent read/write and local constraints
2014-10-02 14:35:59 -04:00
079ed0ffb3
ad_serdes_in: Update the serdes_in module
...
Add additional IDELAY block before the ISERDES. Delet the IDDR blocks. Be aware, the ISERDES block are running in DDR mode. If the interface is SDR the maximum parallel data width is 4.
2014-09-25 16:40:29 +03:00
27ffff827a
common: Initial check in of ad_serdes_in.v
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A generic serdes module for input interface, support both 6 and 7 series.
2014-09-24 18:34:40 +03:00
5af2474d51
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
2014-09-23 22:44:33 -04:00
b877cea2ed
up_axi: Add parameter to configure the internal address width
...
Not all peripherals need 14 bit of address space.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:40 +02:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
...
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
6ad589475a
up_axi: Prevent read and write requests from racing against each other
...
Make sure that if a read and a write request arrive on the very same clock
cycle to only accept one of them. The simple solution chosen here is to only
accept the write request when this happens and delay the acceptance of the
read request until the write request is finished.
This solution is not fair since a write request will always take precedence,
which in theory allows the write bus to starve the read bus. But in practice
we should never see that many write requests that we are unable to answer
the read request.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:04:05 +02:00
18a506b3ca
up_axi: Wait for the transaction to fully finish before releasing up_axi_access
...
Wait for the master to accept the response for the current transaction
before we allow a new transaction to start.
This fixes problems in case the master is not ready to accept the response
when we make it available.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:03:52 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
a773cc4992
usdrx1: updated project
...
ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
2014-09-01 15:18:39 +03:00
2b15c7313e
ad_dcfilter: Fix filter loopback
2014-08-12 14:42:10 +03:00
701dc96016
up_dac_channel: make iq cor coeff(s) tc
2014-07-24 10:10:24 -04:00
db1c931736
ad9625_plddr: PL DDR3 fixes
...
- Modified the axi slave interface handler
- Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
2955b9db78
fifo2s: flush if no request, c5soc: 14.0
2014-07-15 16:25:33 -04:00
e7d5d79e42
daq2/kcu105: gth up and running - as it is commit
2014-07-10 10:56:37 -04:00
a9992f02b0
fifo2s: bug fixes- on 64mhz dma clock
2014-07-08 16:57:44 -04:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
60dd14bcdb
a5soc: removed jtag master control
2014-07-01 12:27:37 -04:00
b6052773b7
added adc/dac gpio registers
2014-06-27 14:45:58 -04:00
6b3312bbf9
library: register map changes and for mathworks
2014-06-24 14:24:22 -04:00
d4be46cc17
library: register map changes and for mathworks
2014-06-24 14:23:56 -04:00
cf56a568c6
kcu105: GTH updates
2014-06-05 14:27:38 -04:00
842cd98b61
ad9361: adc loopback option
2014-05-27 12:15:02 -04:00
0cd43e34f5
dds: zero scale fix
2014-05-21 11:54:49 -04:00
3aed3ba71c
axi_ad9361: fmcomms5 changes
2014-05-19 12:41:12 -04:00
f3f8374c75
ad9671: 2lane version
2014-05-08 18:33:26 -04:00
5f2fb45b24
library: ported hdmi tx to altera
2014-05-02 12:07:47 -04:00
503096de18
gt: change userready on drp clock
2014-04-17 16:09:55 -04:00
c73390b6c9
axi_ad9361: Intermediary check in for altera porting
...
This is work in progress. It will not work as it is
2014-04-11 17:40:34 +03:00
799d2384d8
up_xfer_cntrl: Remove extra semicolon
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
f8f2684b7e
up_gt: eyescan delay bug fix
2014-04-02 16:45:41 -04:00
2472d61daf
ad_gt_es: status asserted early for latency
2014-04-01 15:06:51 -04:00
724bd70a06
altera additions and replacements
2014-04-01 11:18:10 -04:00
25f416e46f
dds output is reset if disabled
2014-03-31 10:01:49 -04:00
ad491e92ab
changed pcore version and made it local (top shouldn't override)
2014-03-14 12:02:16 -04:00
fd14607da5
mult instances: consistent naming style
2014-03-12 15:42:47 -04:00
7fc5b8ecd9
common: use dsp slice for multiply modules
2014-03-12 15:35:21 -04:00
0817973cc0
library: removed xilinx dc filter and dds
2014-03-10 14:52:48 -04:00
bb0431d3e8
library: dds and dcfilter changes, added fifo wrappers
2014-03-10 11:11:50 -04:00
d6256e9e29
library: dds and dcfilter changes, added fifo wrappers
2014-03-10 11:11:16 -04:00
23a62a92b2
up_adc_common: dma bus width is 0x8 (constant)
2014-03-06 19:22:19 -05:00
f7c9368abc
initial checkin
2014-02-28 14:26:22 -05:00
Rejeesh Kutty
Istvan Csomortani
Lars-Peter Clausen
Adrian Costina
U-ANALOG\ACostina