10d9de39a1
axi_ad9361/tdd: Update the synchronization logic
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The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
bcee3e04d4
fmcomms2_tdd: Update tdd_enabaled path
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This line controls the mux, which switch between hdl and software (GPIO) control of the ENABLE/TXNRX pins.
Fix the broken path and change the name from "tdd_enable" to "tdd_enabled".
2015-08-19 12:14:05 +03:00
8e536ad8d1
axi_ad9361: Update Make file
2015-08-19 12:14:03 +03:00
e64baad54a
axi_dmac: Fix a bug occuring on transfers < one beat
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Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2015-08-19 10:23:26 +02:00
e221c3b48c
daq2- gt changes
2015-08-17 14:11:58 -04:00
c72cf99562
daq2- gt changes
2015-08-17 14:11:58 -04:00
b84afcdcd1
Merge branch 'master' into dev
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Conflicts:
library/Makefile
library/axi_ad6676/axi_ad6676_ip.tcl
library/axi_ad9122/axi_ad9122_core.v
library/axi_ad9122/axi_ad9122_ip.tcl
library/axi_ad9144/axi_ad9144_ip.tcl
library/axi_ad9152/axi_ad9152_ip.tcl
library/axi_ad9234/axi_ad9234_ip.tcl
library/axi_ad9250/axi_ad9250_hw.tcl
library/axi_ad9250/axi_ad9250_ip.tcl
library/axi_ad9361/axi_ad9361.v
library/axi_ad9361/axi_ad9361_dev_if_alt.v
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_ad9361/axi_ad9361_rx_channel.v
library/axi_ad9361/axi_ad9361_tdd.v
library/axi_ad9361/axi_ad9361_tx_channel.v
library/axi_ad9625/axi_ad9625_ip.tcl
library/axi_ad9643/axi_ad9643_channel.v
library/axi_ad9643/axi_ad9643_ip.tcl
library/axi_ad9652/axi_ad9652_channel.v
library/axi_ad9652/axi_ad9652_ip.tcl
library/axi_ad9671/axi_ad9671_constr.xdc
library/axi_ad9671/axi_ad9671_ip.tcl
library/axi_ad9680/axi_ad9680_ip.tcl
library/axi_ad9739a/axi_ad9739a_ip.tcl
library/axi_dmac/axi_dmac_constr.sdc
library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
library/axi_jesd_gt/axi_jesd_gt_constr.xdc
library/axi_jesd_gt/axi_jesd_gt_ip.tcl
library/axi_mc_speed/axi_mc_speed_constr.xdc
library/common/ad_gt_channel_1.v
library/common/ad_gt_common_1.v
library/common/ad_gt_es.v
library/common/ad_iqcor.v
library/common/ad_jesd_align.v
library/common/ad_rst.v
library/common/altera/ad_xcvr_rx_rst.v
library/common/up_adc_common.v
library/common/up_axis_dma_rx.v
library/common/up_axis_dma_tx.v
library/common/up_clkgen.v
library/common/up_clock_mon.v
library/common/up_dac_common.v
library/common/up_gt.v
library/common/up_hdmi_tx.v
library/common/up_tdd_cntrl.v
library/common/up_xfer_cntrl.v
library/common/up_xfer_status.v
library/util_cpack/util_cpack.v
library/util_cpack/util_cpack_ip.tcl
library/util_dac_unpack/util_dac_unpack_hw.tcl
library/util_jesd_align/util_jesd_align.v
library/util_jesd_xmit/util_jesd_xmit.v
library/util_upack/util_upack_ip.tcl
library/util_wfifo/util_wfifo.v
library/util_wfifo/util_wfifo_constr.xdc
library/util_wfifo/util_wfifo_ip.tcl
projects/arradio/c5soc/system_bd.qsys
projects/common/vc707/vc707_system_bd.tcl
projects/common/zc706/zc706_system_plddr3.tcl
projects/daq2/a10gx/Makefile
projects/daq2/a10gx/system_bd.qsys
projects/daq3/common/daq3_bd.tcl
projects/daq3/zc706/system_bd.tcl
projects/fmcjesdadc1/a5gt/Makefile
projects/fmcjesdadc1/a5gt/system_bd.qsys
projects/fmcjesdadc1/a5gt/system_constr.sdc
projects/fmcjesdadc1/a5gt/system_top.v
projects/fmcjesdadc1/a5soc/system_bd.qsys
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms1/ac701/system_bd.tcl
projects/fmcomms1/common/fmcomms1_bd.tcl
projects/fmcomms1/kc705/system_bd.tcl
projects/fmcomms1/vc707/system_bd.tcl
projects/fmcomms1/zc702/system_bd.tcl
projects/fmcomms1/zc702/system_top.v
projects/fmcomms1/zc706/system_bd.tcl
projects/fmcomms1/zc706/system_top.v
projects/fmcomms1/zed/system_bd.tcl
projects/fmcomms1/zed/system_top.v
projects/fmcomms2/ac701/system_constr.xdc
projects/fmcomms2/common/fmcomms2_bd.tcl
projects/fmcomms2/kc705/system_constr.xdc
projects/fmcomms2/kc705/system_top.v
projects/fmcomms2/mitx045/system_top.v
projects/fmcomms2/rfsom/system_constr.xdc
projects/fmcomms2/rfsom/system_top.v
projects/fmcomms2/vc707/system_top.v
projects/fmcomms2/zc706/system_bd.tcl
projects/fmcomms2/zc706/system_constr.xdc
projects/fmcomms2/zc706/system_top.v
projects/fmcomms2/zed/system_top.v
projects/imageon/zc706/system_constr.xdc
projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
projects/motcon2_fmc/zed/system_constr.xdc
projects/motcon2_fmc/zed/system_top.v
projects/usdrx1/a5gt/Makefile
projects/usdrx1/a5gt/system_bd.qsys
projects/usdrx1/common/usdrx1_bd.tcl
Conflicts were resolved using 'Mine' (/dev).
2015-08-17 15:15:58 +03:00
50d1a6dcca
Merge branch 'master' into hdl_2015_r1
2015-08-17 10:45:05 +03:00
17b2a9f121
Merge branch 'master'
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Merge master into release to sync the index files. The two changes are just mode changes. There aren't any functional changes in this commit!
2015-08-17 10:09:07 +03:00
c22d1c044b
axi_jesd_gt-- gt interfaces
2015-08-14 15:34:49 -04:00
890f743f1a
util_jesd_gt-- gt interfaces
2015-08-14 15:34:30 -04:00
6eb0b5eeda
scripts-- add interface procedures
2015-08-14 15:33:58 -04:00
2345be2237
interfaces-- transceiver cores
2015-08-14 15:33:36 -04:00
8bb68af29d
ignore xml files
2015-08-14 15:33:11 -04:00
af87b65788
interfaces_ip: added
2015-08-14 11:24:27 -04:00
4643dab62d
Merge branch 'hdl_2015_r1'
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Conflicts:
projects/ad9671_fmc/common/ad9671_fmc_bd.tcl
projects/ad9671_fmc/zc706/system_top.v
projects/cftl_std/zed/system_project.tcl
projects/motcon1_fmc/zed/system_project.tcl
projects/motcon2_fmc/zed/system_project.tcl
projects/motcon2_fmc/zed/system_top.v
2015-08-14 10:44:36 +03:00
ebecfde64c
axi_hdmi_tx: common constraints & async resets
2015-08-13 13:03:51 -04:00
a6f6c81795
axi_jesd_gt- gt lane split
2015-08-13 13:03:51 -04:00
041be729f6
common/ip-constrs- uniform simple constraints will do
2015-08-13 13:03:51 -04:00
a2b816beda
common/up_hdmi_tx: wrong clock on vdma status signals
2015-08-13 13:03:51 -04:00
5edf61c40a
ad_rst:- allow preset to be synchronized as reset
2015-08-13 13:03:51 -04:00
2bcac36e33
common/up_- change to asynchronous resets
2015-08-13 13:03:51 -04:00
2b8e1bdb74
adi_ip- parse file list for constraints
2015-08-13 13:03:51 -04:00
3615c9cad7
axi_jesd_gt- bug fixes
2015-08-13 13:03:51 -04:00
44d51e665d
util_jesd_gt- port type fix
2015-08-13 13:03:51 -04:00
8697b0a8d6
axi_jesd_gt- ip script changes
2015-08-13 13:03:51 -04:00
e265ca9ea7
util_jesd_gt- ip tcl changes
2015-08-13 13:03:51 -04:00
a108ca9309
util_jesd_gt- updates
2015-08-13 13:03:51 -04:00
a4076424e0
util_jesd_gt- added
2015-08-13 13:03:51 -04:00
10d4da64dd
axi_jesd_gt: move master/slave control to a util module
2015-08-13 13:03:51 -04:00
3ed350efbc
axi_jesd_gt- split up
2015-08-13 13:03:51 -04:00
e4f94664a6
axi_jesd_gt- remove per lane control/status to channel
2015-08-13 13:03:51 -04:00
f807490ed1
axi_jesd_gt- per lane group
2015-08-13 13:03:51 -04:00
4c8206608c
axi_jesd_gt- separate es-axi
2015-08-13 13:03:51 -04:00
e4b0710923
axi_jesd_gt- per lane split-up
2015-08-13 13:03:51 -04:00
f08633c0d5
fmcomms2: Add GPIO to the c5soc project
2015-08-13 18:14:39 +03:00
eaddde1ea4
README.md: Update to Quartus 15.0. Removed release candidate note
2015-08-13 11:55:23 +03:00
ce26373e8a
axi_ad9671: updated constraints to apply in all cases
2015-08-13 11:53:15 +03:00
c200fc8019
usdrx1: Updated a5gt project to Quartus 15
2015-08-12 10:20:58 +03:00
0379279bd4
axi_ad9671: Fixed rx_sof pin name
2015-08-12 10:20:09 +03:00
489b31e929
ad9434_fmc: DMAC's destination clock must be more than or equal to adc_clk/4 (125 Mhz)
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DMAC's destination clock set to 200Mhz
2015-08-10 18:00:24 +03:00
10a3ce96fe
ad9434_fmc: DMAC's destination clock must be more than or equal to adc_clk/4 (125 Mhz)
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DMAC's destination clock set to 200Mhz
2015-08-10 17:57:52 +03:00
afb9911b6e
Makefiles: Updated makefiles
2015-08-06 19:50:50 +03:00
f59058dd8a
axi_ad9434: Fix the up interface for IO_DELAYs
2015-08-06 15:17:19 +03:00
ad80561379
TDD_regmap: Fix CDC for control signals
2015-08-06 15:16:39 +03:00
e19d476b58
TDD_regmap: Fix addresses
2015-08-06 15:15:50 +03:00
d2c99acae8
fmcomms2/TDD: Update synchronization interface
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Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
6104061d19
axi_ad9434: Fix the up interface for IO_DELAYs
2015-08-04 13:46:15 +03:00
cfc4046821
fmcomms2: Add a synchronization interface for TDD mode.
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Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-29 14:10:56 +03:00
ed6bdf66bd
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
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Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-29 11:59:17 +03:00
Istvan Csomortani
Paul Cercueil
Rejeesh Kutty
Adrian Costina