a31cb6c475
axi_i2s/axi_spdif: Remove manual creation of Streaming AXI bus
...
It looks like Vivado is now able to infer these buses from the sources.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:06 +03:00
4bdb3cd262
axi_ad9671: altera axi4lite changes
2014-10-09 15:25:07 -04:00
6125bbecc3
axi_ad9671: altera axi4lite changes
2014-10-09 15:25:06 -04:00
2817ccdb22
up_axi: altera can not handle same clock assertion of arready and rvalid
2014-10-09 15:25:05 -04:00
5565cf8fad
axi_ad9467: Independent read/write update
...
Independent read/write operation is supported on "up" interface
2014-10-08 11:23:44 +03:00
88a3b7f8fd
library: remove all constraints for now
2014-10-07 16:59:19 -04:00
2dfcb0c599
usdrx1: Initial commit for a5gt
...
axi_ad9671: added start of frame information to the altera core.
2014-10-07 19:41:54 +03:00
a436153a48
axi_ad9434: Independent read/write update
...
Independent read/write is supported on "up" interface.
2014-10-07 18:01:44 +03:00
9404e93126
ad9434_fmc: Fix PN monitor.
...
No need to flop the incoming data.
2014-10-07 17:56:27 +03:00
66baf6ac3e
axi_ad9434: Deleted unused ip file
...
ad_lvds_in.v is not used in this ip core.
2014-10-07 17:47:08 +03:00
bfa17844ff
ad_serdes_in: General update
...
Added a parameter for option SDR / DDR mode, added a parameter for parallel data width.
Note: default IF_TYPE is SDR and default PARALLEL_WIDTH is 8
2014-10-07 17:42:27 +03:00
151781a2af
axi_ad9467: Fix PN sequence checker
...
Make sure that the reference PN sequence is only incremented every two clock
cycles to make sure that it matches the rate of the ADC PN sequence.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-07 16:26:53 +03:00
59640f181b
ad9467: Fix LVDS delay interface.
2014-10-07 16:25:22 +03:00
c375b5b26e
daq3: vivado build
2014-10-06 10:34:02 -04:00
d47776a4a0
ad9152: 9144 copy
2014-10-06 10:34:01 -04:00
581892b22a
axi_ad9265: Updated project with new up independent read/write
2014-10-03 12:32:08 +03:00
de33722470
up/constr: independent read/write and local constraints
2014-10-02 14:35:59 -04:00
922bc6f03a
fmcadc3: 16bit - but ignored 4 lsb(s)
2014-09-29 15:26:30 -04:00
6a09a1ed19
ad9434: Fix the processor read interface
...
Fix the processor read interface, preventing to have nets with multiple drivers. Made a few cosmetic changes in the code too.
2014-09-25 16:51:58 +03:00
ccb0b135ca
ad9434: Fix the adc to dma interface.
...
All the device2dma interfaces needs to have a generic form : (data, enable, valid)/channel
2014-09-25 16:50:09 +03:00
d5f4991e26
ad9434: Merge the ad9434_if interface data outputs into one single bus
2014-09-25 16:45:12 +03:00
079ed0ffb3
ad_serdes_in: Update the serdes_in module
...
Add additional IDELAY block before the ISERDES. Delet the IDDR blocks. Be aware, the ISERDES block are running in DDR mode. If the interface is SDR the maximum parallel data width is 4.
2014-09-25 16:40:29 +03:00
27ffff827a
common: Initial check in of ad_serdes_in.v
...
A generic serdes module for input interface, support both 6 and 7 series.
2014-09-24 18:34:40 +03:00
683561b67d
AD9434: Initial check in of the library and project with ZC706
2014-09-24 18:27:17 +03:00
1d4bc47cea
ad9265: Initial commit
2014-09-23 22:51:42 -04:00
5af2474d51
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
2014-09-23 22:44:33 -04:00
1682d9da10
fmcadc3: initial updates
2014-09-22 11:27:17 -04:00
e528ee0b52
axi_ad9234: axi_ad9680 copy
2014-09-22 11:27:15 -04:00
de0edc2083
axi_dmac: src_fifo_inf: Clear pipeline when no transfers are active
...
Clear the pipeline when no transfers are active to make sure that we do not
get residual data on the first sample for the next transfer.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-16 21:02:05 +02:00
c927e90ee1
axi_dmac/axi_fifo: Add missing file
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-15 21:04:57 +02:00
17a993032b
util_dac_unpack: Make number of channels and channel width configurable
...
Always using 128bit for the input word unnecessarily increases the DMA
alignment requirements. This breaks existing software which assumes that the
DMA alignment requirement is 64bit.
So make it configurable whether we want 8 or 4 channels and while we are at
it also make the channel width configurable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:14:04 +02:00
61f21a17b3
fmcomms2:c5soc project upgraded with util_dac_unpack
2014-09-11 15:13:09 -04:00
3162540b03
axi_ad9361: Remove the Altera toplevel wrapper
...
By setting the AXI controler interface type from axi4 to axi4lite we can use
the normal toplevel file with only a simple modification to add the awprot
and arprot signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:29:13 +02:00
36422f0454
axi_dmac: Remove Altera toplevel wrapper
...
We can remove the Altera toplevel wrapper if we switch the axi4 control bus
to axi4lite and add the few missing signals that are required by the Altera
interconnect to both the control and the data buses.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:28:14 +02:00
b877cea2ed
up_axi: Add parameter to configure the internal address width
...
Not all peripherals need 14 bit of address space.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:40 +02:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
...
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
6ad589475a
up_axi: Prevent read and write requests from racing against each other
...
Make sure that if a read and a write request arrive on the very same clock
cycle to only accept one of them. The simple solution chosen here is to only
accept the write request when this happens and delay the acceptance of the
read request until the write request is finished.
This solution is not fair since a write request will always take precedence,
which in theory allows the write bus to starve the read bus. But in practice
we should never see that many write requests that we are unable to answer
the read request.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:04:05 +02:00
18a506b3ca
up_axi: Wait for the transaction to fully finish before releasing up_axi_access
...
Wait for the master to accept the response for the current transaction
before we allow a new transaction to start.
This fixes problems in case the master is not ready to accept the response
when we make it available.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:03:52 +02:00
0da7b6eaa1
axi_dmac: axi_dmac_alt.v: Set default transfer length width to 24
...
This is the same as the default value in axi_dmac.v
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:07:35 +02:00
a4b9b1254a
axi_ad9361/axi_dmac: Fix altrea AXI wrapper rid/wid handling
...
We must make sure that the response ID is the same as the request ID when we
accepted the request. Otherwise we might respond with the wrong ID and the
system will lockup.
Also set rlast to 1 instead of 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
0966366514
motor_control: Updated the FOC IP
2014-09-08 15:52:18 +03:00
6e389b8c47
motor_control: Updated the FOC IP and the encoder connections to the IP
2014-09-06 15:58:03 +03:00
acde4f2c9a
axi_dmac: Added fix to work with motor_control
2014-09-03 12:10:34 +03:00
dfb94f7b68
motor_control: Modified foc_controller to be compatible with other cores
2014-09-03 12:09:37 +03:00
d08d0cd70b
motor_control: added the MW FOC IP and updated the design
2014-09-01 18:35:21 +03:00
a773cc4992
usdrx1: updated project
...
ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
2014-09-01 15:18:39 +03:00
cf660c126d
util_adc_pack: Fixed problems when working in 4 channels mode
2014-08-29 13:51:40 +03:00
da913864c9
ad9671_fmc: updates to match recent core changes
2014-08-28 13:16:52 -04:00
272874f6ad
ad9652: pnmon fixes
2014-08-27 10:44:38 -04:00
31002c404c
util_adc_pack: Added parameters for configuring data width and number of channels
...
Valid values for the number of channels is 4 or 8
Valid values for datawidth is 16 or 32
2014-08-27 14:47:57 +03:00
58fa0776c9
axi_dmac: Added patch to fix issue on altera systems
2014-08-26 16:24:34 +03:00
5f21f54463
fmcjesdadc1: zc706 version
2014-08-25 14:28:57 -04:00
fe1eaefcff
fmcomms1: zc706
2014-08-22 09:08:55 -04:00
280260e54c
c5soc: dmac separated slave and master id widths
2014-08-22 09:08:54 -04:00
b481df0b5f
library: local constraints async groups
2014-08-14 15:09:51 -04:00
01963b01fc
jesd_gt: local constraints
2014-08-14 15:09:49 -04:00
9438e2a9e0
spdif: constraints file added
2014-08-14 15:09:48 -04:00
1396a215e5
library: local constraints
2014-08-14 15:09:47 -04:00
39bb7ca231
a5soc: fmcjesdadc1+hdmi version
2014-08-14 09:05:38 -04:00
2b15c7313e
ad_dcfilter: Fix filter loopback
2014-08-12 14:42:10 +03:00
a5e3a07375
dma: altera fix id assignments
2014-08-11 16:46:36 -04:00
9dfbf4a9a6
prcfg: Update the prcfg logic to the new ad9361 interface
2014-08-05 17:54:37 +03:00
08a12aaf23
library: register map updates on 9467, 9643 and 9671
2014-07-31 15:19:45 -04:00
dfd11cb809
ad9467: register map changes
2014-07-30 15:31:09 -04:00
c215eab696
ad9122: register map updates
2014-07-30 11:32:15 -04:00
b97bdcdc23
ad9122: register map updates
2014-07-30 11:32:13 -04:00
a2b728b91e
util_adc_pack: added extra registers to meet timing.
...
Util_dac_unpack: fixed issue regarding changing from 1 channel to 2
2014-07-25 17:41:47 +03:00
26a019ae6e
util_adc_pack: Fixed issue regarding changing from 1 channel to 2
2014-07-25 10:20:49 +03:00
59759a8ab3
c5soc: working hdl version
2014-07-24 20:51:41 -04:00
6346017763
c5soc: changed to alt_lvds - 250M is too high for cyclone v
2014-07-24 20:51:40 -04:00
7000897031
fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
...
The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
2014-07-24 19:57:22 +03:00
701dc96016
up_dac_channel: make iq cor coeff(s) tc
2014-07-24 10:10:24 -04:00
191f994e79
prcfg: Fixed the PRBS lock issue on BIST
2014-07-24 09:41:13 +03:00
db1c931736
ad9625_plddr: PL DDR3 fixes
...
- Modified the axi slave interface handler
- Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
4da8100fe5
ad9625_plddr: Delete trailing whitespaces.
2014-07-23 19:31:07 +03:00
54b2cd74bf
motor_control: cores modified so they can compile with the new common files
2014-07-23 11:58:50 +03:00
c0e31aa6c2
daq2: latest hardware
2014-07-21 09:06:57 -04:00
2955b9db78
fifo2s: flush if no request, c5soc: 14.0
2014-07-15 16:25:33 -04:00
e7d5d79e42
daq2/kcu105: gth up and running - as it is commit
2014-07-10 10:56:37 -04:00
a9992f02b0
fifo2s: bug fixes- on 64mhz dma clock
2014-07-08 16:57:44 -04:00
b434fe6dd5
fmcomms5: register map changes
2014-07-08 16:57:43 -04:00
dc78ced443
prcfg_lib: Change the prcfg_top interface
...
Use the device core's gpio_input and gpio_output registers to get/set
status and control of PR.
2014-07-08 12:28:25 +03:00
75e624ef15
prcfg_lib: Flop the status and mode nets
...
Flop the status and mode nets in case of BIST and QPSK configurations.
2014-07-08 12:23:48 +03:00
39ac29bb01
AD9361: Altera, modified address width so that all registers are accessible
...
Modified qsys project with the new address span
2014-07-08 10:41:51 +03:00
f3b20fd148
axi_ad9625: register map updates
2014-07-03 11:19:31 -04:00
1a78ac453e
Merge branch 'devel' of github.com:analogdevicesinc/hdl into devel
2014-07-02 15:39:42 -04:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
e4ce00f7fb
axi_ad9680: register map changes
2014-07-02 12:50:09 -04:00
7e5748374d
prcfg_lib: Fixed prbs generator for QPSK
2014-07-02 18:14:35 +03:00
8eb7a55797
prcfg_lib: Fixed the gpio status merge logic
...
The previous logic did not passed implementation.
2014-07-02 18:09:48 +03:00
9089877c70
prcfg_lib: Fixed the sine tone generator for BIST
2014-07-02 18:00:43 +03:00
8a2b29cdbe
axi_damc: Add xfer_req to the FIFO source interface
...
The xfer_req signal will be high if DMA core the is expecting data.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-07-02 16:05:16 +02:00
31abd07613
axi_ad9144: register map changes
2014-07-01 21:43:04 -04:00
60dd14bcdb
a5soc: removed jtag master control
2014-07-01 12:27:37 -04:00
b6052773b7
added adc/dac gpio registers
2014-06-27 14:45:58 -04:00
ba7955c531
fmcomms2: register map modifications
2014-06-26 10:09:03 -04:00
4afe6c24e9
Merge branch 'devel' of github.com:analogdevicesinc/hdl into devel
2014-06-25 15:26:21 -04:00
10a7804e14
ad9361: altera wrapper updates
2014-06-25 15:26:06 -04:00
4fdb3cfc4a
ad9250: register map updates
2014-06-25 15:23:57 -04:00
4f5d163fcc
Merge branch 'master' into devel
2014-06-25 13:07:12 -04:00
e38813fa9f
fifo- monitor status signals
2014-06-25 12:15:13 -04:00
4877df9bec
axi_fifo2s: make read dead slow
2014-06-25 09:20:57 -04:00
985ace533e
ad9361: remove unused modules
2014-06-24 14:26:40 -04:00
6b3312bbf9
library: register map changes and for mathworks
2014-06-24 14:24:22 -04:00
d4be46cc17
library: register map changes and for mathworks
2014-06-24 14:23:56 -04:00
e650253013
library: register map changes and for mathworks
2014-06-24 14:22:05 -04:00
89961c8dd7
prcfg_lib: Update the PR libraries
...
+ Flop the control nets too inside the adc/dac module
+ Flop the gpio_out in prcfg_top
2014-06-13 20:35:35 +03:00
7efd6149f8
daq2: initial checkin
2014-06-12 15:54:25 -04:00
87bec07a22
ad9625: added multi-sync support
2014-06-12 15:45:34 -04:00
5189d200e7
axi_fifo2s: linux fix on interfaces
2014-06-12 15:30:13 -04:00
3e5990366e
axi_ad9625: initial release
2014-06-09 16:39:08 -04:00
bef6a9c32c
axi_ad9361: Split dma data into individual channels for both ADC and DAC
2014-06-07 17:15:31 +03:00
cf56a568c6
kcu105: GTH updates
2014-06-05 14:27:38 -04:00
ea22d29862
prcfg: Initial check in of PR modules
...
Initial check in of the partial reconfiguraiton modules.
2014-06-05 14:58:14 +03:00
5b5bca400f
ad9361: added adc loopback
2014-05-27 14:47:59 -04:00
842cd98b61
ad9361: adc loopback option
2014-05-27 12:15:02 -04:00
56ddce1e8c
dmac: create fifo interface to avoid being treated as axi control stream
2014-05-27 10:25:14 -04:00
0cd43e34f5
dds: zero scale fix
2014-05-21 11:54:49 -04:00
916afd460f
axi_jesd_gt: synchronization support
2014-05-19 14:17:31 -04:00
3aed3ba71c
axi_ad9361: fmcomms5 changes
2014-05-19 12:41:12 -04:00
f73819f4d4
zc706: pl ddr3 initial checkin
2014-05-13 16:19:53 -04:00
a007add714
iqcorrection: missing input signals fix
2014-05-09 11:17:50 -04:00
f3f8374c75
ad9671: 2lane version
2014-05-08 18:33:26 -04:00
1d50489870
ad9361: ml605 updates
2014-05-05 11:03:57 -04:00
5f2fb45b24
library: ported hdmi tx to altera
2014-05-02 12:07:47 -04:00
a10043c4f4
kcu105: base complete with ethernet errors
2014-04-30 14:41:43 -04:00
ef60cce15e
kcu105: added
2014-04-30 14:41:40 -04:00
f55288ef5d
ad9671: altera - base changes
2014-04-28 21:31:18 -04:00
02e8b27626
initial checkin-9250 copy
2014-04-28 21:31:16 -04:00
01de117b5f
motor_control: Changed controller to PID controller. Some estetic changes
2014-04-28 17:57:51 +03:00
fa998a406b
dma: parameter fix
2014-04-24 15:50:16 -04:00
314ec3d343
altera-9250/dma: make id width generic
2014-04-24 14:54:19 -04:00
dfc2bba335
ad9671: updates to allow default adc setup routines
2014-04-23 16:39:28 -04:00
213e852e11
motor_control: Initial commit
2014-04-18 18:57:18 +03:00
503096de18
gt: change userready on drp clock
2014-04-17 16:09:55 -04:00
570ec26798
FMCOMMS2: Added sync option
2014-04-11 18:14:48 +03:00
99ef34936f
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-11 18:14:08 +03:00
c73390b6c9
axi_ad9361: Intermediary check in for altera porting
...
This is work in progress. It will not work as it is
2014-04-11 17:40:34 +03:00
af07f8874f
wfifo/rfifo: asynchronous interface
2014-04-10 14:01:40 -04:00
96541f0a7f
usdrx1: zc706 updated for usdrx1
2014-04-10 11:05:13 -04:00
dc7b3e085c
axi_dmac: Fix issues with non 64-bit AXI masters
...
Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:54:22 +02:00
36ef882da0
axi_dmac: data_mover: Improve timing
...
We do not know which 'last' condition to use before hand, but we can pre-compute
the result for both conditions and then use them. This removes the comparison
from the already pretty long combinatorial path.
Also simplify a few expressions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:06:44 +02:00
090d3aee04
axi_dmac: Change C_DMA_LENGTH_WIDTH default to 24
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
cb630e36a9
axi_dmac: src_fifo_inf: Simplify data path
...
Improves timing a bit
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
f9ca4fb8be
axi_fifo: Slightly improve timing
...
It is OK to overwrite invalid data with other invalid data.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
4c9647f289
axi_dmac: axi_register_slice: Provide default values for registers
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
fa5ba6c09d
axi_dmac: Make cyclic mode runtime configurable
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
7ca43f4920
axi_dmac: address_generator: Make 'len' registered
...
Slightly improves the timing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
66e6c1cc21
axi_dmac: axi_register_slice: Remove reset "latch" from datapath
...
Move the datapath updates out of the else branch of the reset condition.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
acozma
ATofan
U-ANALOG\ACostina