2 Commits (95c98c634e4283a7d05c45bb3e3a2be94c6c82da)

Author	SHA1	Message	Date
Lars-Peter Clausen	95c98c634e	axi_dmac: Split transfer handling into separate sub-module ... Move the transfer logic, including the 2d module, into its own sub-module. This allows testing of the full transfer logic independently of the register map logic. The top-level module now only instantiates the register map and transfer module, but does not have any logic on its own. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2018-07-03 13:44:34 +02:00
Lars-Peter Clausen	24d17e8bcc	axi_dmac: Add transfer testbenches ... Add simple transfer testbenches that test the read and write to AXI memory paths of the DMAC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2018-05-03 14:49:06 +02:00