Istvan Csomortani
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b9d3039568
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axi_dacfifo: Register the dac_valid signals
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2017-02-24 12:34:58 +02:00 |
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Istvan Csomortani
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debc6e2066
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axi_dacfifo: Data from DMA is validated with dma_ready too
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2017-02-24 12:32:25 +02:00 |
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Istvan Csomortani
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dfcd5214a0
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axi_dacfifo: axi_dvalid should come from dacfifo_rd module
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2017-02-24 12:28:46 +02:00 |
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Istvan Csomortani
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1fce57f6c3
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axi_dacfifo: Redesign the bypass functionality
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2017-02-23 17:32:31 +02:00 |
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Istvan Csomortani
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e3ac341aad
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axi_dacfifo: Fix constraints
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2017-02-21 14:45:18 +02:00 |
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Istvan Csomortani
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981a61bf16
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axi_dacfifo: Clean up the axi_dacfifo_wr.v module
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2017-02-17 18:40:02 +02:00 |
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Istvan Csomortani
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f10866e4c3
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axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter
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2017-02-16 19:54:41 +02:00 |
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Istvan Csomortani
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95a4ea20c8
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axi_dacfifo: Delete redundant parameter BYPASS_EN
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2017-02-16 19:53:44 +02:00 |
Adrian Costina
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8ebc8fe4e2
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updated makefiles
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2016-12-09 23:06:41 +02:00 |
Rejeesh Kutty
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9defccef70
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dacfifo- axi address map fixes
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2016-09-27 14:48:23 -04:00 |
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Istvan Csomortani
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3b0c1e02fc
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axi_dacfifo: Move IP to library/xilinx
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2016-09-15 11:38:16 +03:00 |