Commit Graph

96 Commits (940c3ccd35c802b011833e3ba2674d8e71cc9ff6)

Author SHA1 Message Date
Rejeesh Kutty 6decba3c3b hdlmake.pl updates 2017-06-09 16:23:17 -04:00
Rejeesh Kutty f3af192f30 altera 16.1 arradio updates 2017-06-08 15:02:46 -04:00
Rejeesh Kutty dd48929327 hdlmake.pl - updates 2017-06-06 12:25:35 -04:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 4c998d1e18 make: Update make files 2017-05-25 15:12:17 +03:00
Lars-Peter Clausen 01aea161fa Create CDC helper library
Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Adrian Costina 942d69a30c Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
Rejeesh Kutty d84e34fe5f arradio/c5soc- reset false path for vga dma 2017-03-21 10:15:38 -04:00
Rejeesh Kutty 8063ba2b66 make updates 2017-03-20 16:05:18 -04:00
Rejeesh Kutty c7351f3ce3 arradio/c5soc- remove qsys files 2017-03-20 15:56:07 -04:00
Rejeesh Kutty 589e6b53d8 arradio/c5soc- qsys-script flow 2017-03-20 15:42:33 -04:00
Rejeesh Kutty 7dfa8c599f arradio/c5soc- updated to new framework/16.0 2017-03-20 12:15:18 -04:00
Adrian Costina 8ebc8fe4e2 updated makefiles 2016-12-09 23:06:41 +02:00
Rejeesh Kutty 0dfbb0af11 arradio/c5soc- constraints changes- interface 1r1t 2016-11-03 11:25:52 -04:00
Rejeesh Kutty 671a547c2b hdlmake- updates 2016-11-01 12:41:25 -04:00
AndreiGrozav b8363d778d arradio: Makefile update 2016-10-25 20:36:56 +03:00
Rejeesh Kutty cb97bc500a hdlmake updates 2016-10-17 16:29:57 -04:00
Rejeesh Kutty 905e29eb01 hdlmake- altera 2016-10-10 12:55:55 -04:00
Istvan Csomortani 16ee1336c3 Makefile: Update make files 2016-09-15 11:41:06 +03:00
Rejeesh Kutty f697490de6 hdlmake- updates 2016-08-19 15:59:41 -04:00
Adrian Costina 0b0aa8e6c0 Makefile: Add MMU option to altera makefiles 2016-08-11 17:46:54 +03:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
Istvan Csomortani f784557895 lib_refactoring: IOBUF is a Xilinx macro, no need to use with Altera 2016-08-08 15:06:34 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty eaf4d4a19d makefile updates 2016-06-10 14:26:14 -04:00
Rejeesh Kutty 09520709b0 make updates 2016-05-20 12:35:45 -04:00
Rejeesh Kutty 50d018fc11 arradio- rfifo/wfifo added 2016-05-18 13:24:13 -04:00
Rejeesh Kutty e345953bdd arradio- updates 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 0041bf69be c5soc- remove unused hps ports 2016-05-09 13:54:08 -04:00
Istvan Csomortani b0538a03a2 Make: Update 2016-05-06 16:44:24 +03:00
Adrian Costina d94f157454 arradio: Changed ADC/DAC DMA address length to 24 bit 2016-02-16 15:27:51 +02:00
Adrian Costina 43e03ca6f7 arradio: Updated project
- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
2016-02-16 14:50:23 +02:00
Adrian Costina 2309c4d83c Makefiles: Removed " from path 2015-11-27 14:02:46 +02:00
Adrian Costina 159f6c1216 Makefiles: Updated Makefiles
- for altera projects, taken into consideration of the new location for common qsys files
- for fmcomms5, added wfifo dependency
- for daq3, added mfifo dependency
2015-11-27 12:39:42 +02:00
Adrian Costina 605a0768e0 arradio: Updated c5soc project 2015-11-24 13:27:44 +02:00
Adrian Costina 9d2b8809df Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00
Istvan Csomortani a679251d7d Makefiles: Update Make 2015-09-09 17:13:19 +03:00
Istvan Csomortani b84afcdcd1 Merge branch 'master' into dev
Conflicts:
	library/Makefile
	library/axi_ad6676/axi_ad6676_ip.tcl
	library/axi_ad9122/axi_ad9122_core.v
	library/axi_ad9122/axi_ad9122_ip.tcl
	library/axi_ad9144/axi_ad9144_ip.tcl
	library/axi_ad9152/axi_ad9152_ip.tcl
	library/axi_ad9234/axi_ad9234_ip.tcl
	library/axi_ad9250/axi_ad9250_hw.tcl
	library/axi_ad9250/axi_ad9250_ip.tcl
	library/axi_ad9361/axi_ad9361.v
	library/axi_ad9361/axi_ad9361_dev_if_alt.v
	library/axi_ad9361/axi_ad9361_ip.tcl
	library/axi_ad9361/axi_ad9361_rx_channel.v
	library/axi_ad9361/axi_ad9361_tdd.v
	library/axi_ad9361/axi_ad9361_tx_channel.v
	library/axi_ad9625/axi_ad9625_ip.tcl
	library/axi_ad9643/axi_ad9643_channel.v
	library/axi_ad9643/axi_ad9643_ip.tcl
	library/axi_ad9652/axi_ad9652_channel.v
	library/axi_ad9652/axi_ad9652_ip.tcl
	library/axi_ad9671/axi_ad9671_constr.xdc
	library/axi_ad9671/axi_ad9671_ip.tcl
	library/axi_ad9680/axi_ad9680_ip.tcl
	library/axi_ad9739a/axi_ad9739a_ip.tcl
	library/axi_dmac/axi_dmac_constr.sdc
	library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
	library/axi_jesd_gt/axi_jesd_gt_constr.xdc
	library/axi_jesd_gt/axi_jesd_gt_ip.tcl
	library/axi_mc_speed/axi_mc_speed_constr.xdc
	library/common/ad_gt_channel_1.v
	library/common/ad_gt_common_1.v
	library/common/ad_gt_es.v
	library/common/ad_iqcor.v
	library/common/ad_jesd_align.v
	library/common/ad_rst.v
	library/common/altera/ad_xcvr_rx_rst.v
	library/common/up_adc_common.v
	library/common/up_axis_dma_rx.v
	library/common/up_axis_dma_tx.v
	library/common/up_clkgen.v
	library/common/up_clock_mon.v
	library/common/up_dac_common.v
	library/common/up_gt.v
	library/common/up_hdmi_tx.v
	library/common/up_tdd_cntrl.v
	library/common/up_xfer_cntrl.v
	library/common/up_xfer_status.v
	library/util_cpack/util_cpack.v
	library/util_cpack/util_cpack_ip.tcl
	library/util_dac_unpack/util_dac_unpack_hw.tcl
	library/util_jesd_align/util_jesd_align.v
	library/util_jesd_xmit/util_jesd_xmit.v
	library/util_upack/util_upack_ip.tcl
	library/util_wfifo/util_wfifo.v
	library/util_wfifo/util_wfifo_constr.xdc
	library/util_wfifo/util_wfifo_ip.tcl
	projects/arradio/c5soc/system_bd.qsys
	projects/common/vc707/vc707_system_bd.tcl
	projects/common/zc706/zc706_system_plddr3.tcl
	projects/daq2/a10gx/Makefile
	projects/daq2/a10gx/system_bd.qsys
	projects/daq3/common/daq3_bd.tcl
	projects/daq3/zc706/system_bd.tcl
	projects/fmcjesdadc1/a5gt/Makefile
	projects/fmcjesdadc1/a5gt/system_bd.qsys
	projects/fmcjesdadc1/a5gt/system_constr.sdc
	projects/fmcjesdadc1/a5gt/system_top.v
	projects/fmcjesdadc1/a5soc/system_bd.qsys
	projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
	projects/fmcomms1/ac701/system_bd.tcl
	projects/fmcomms1/common/fmcomms1_bd.tcl
	projects/fmcomms1/kc705/system_bd.tcl
	projects/fmcomms1/vc707/system_bd.tcl
	projects/fmcomms1/zc702/system_bd.tcl
	projects/fmcomms1/zc702/system_top.v
	projects/fmcomms1/zc706/system_bd.tcl
	projects/fmcomms1/zc706/system_top.v
	projects/fmcomms1/zed/system_bd.tcl
	projects/fmcomms1/zed/system_top.v
	projects/fmcomms2/ac701/system_constr.xdc
	projects/fmcomms2/common/fmcomms2_bd.tcl
	projects/fmcomms2/kc705/system_constr.xdc
	projects/fmcomms2/kc705/system_top.v
	projects/fmcomms2/mitx045/system_top.v
	projects/fmcomms2/rfsom/system_constr.xdc
	projects/fmcomms2/rfsom/system_top.v
	projects/fmcomms2/vc707/system_top.v
	projects/fmcomms2/zc706/system_bd.tcl
	projects/fmcomms2/zc706/system_constr.xdc
	projects/fmcomms2/zc706/system_top.v
	projects/fmcomms2/zed/system_top.v
	projects/imageon/zc706/system_constr.xdc
	projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
	projects/motcon2_fmc/zed/system_constr.xdc
	projects/motcon2_fmc/zed/system_top.v
	projects/usdrx1/a5gt/Makefile
	projects/usdrx1/a5gt/system_bd.qsys
	projects/usdrx1/common/usdrx1_bd.tcl

Conflicts were resolved using 'Mine' (/dev).
2015-08-17 15:15:58 +03:00
Adrian Costina a7da779b94 Makefile: Updated Makefiles 2015-07-16 18:19:42 +03:00
Istvan Csomortani 46fa91d5be Makefile: Update Make files 2015-07-03 18:08:57 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Adrian Costina 25e56a4d03 arradio: renamed fmcomms2 c5soc to arradio 2015-06-08 11:35:21 +03:00