laurentiu_popa
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7ccc505950
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projects/ad7134_fmc: Add FMC pinout description
* Added txt description of all FMC pins used/unused
* Updated constraint files with FMC pinout location
Signed-off-by: laurentiu_popa <Laurentiu.Popa@analog.com>
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2023-10-19 13:56:12 +03:00 |
Iulia Moldovan
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c9a7d4d927
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Add copyright and license to .tcl, .ttcl files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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2023-07-25 15:22:26 +03:00 |
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laurent-19
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2ae09c9808
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Check guidelines. Remove redundancies
* Removed empty/commented lines
* Regenerated Makefiles
* Removed redundancies adc channels data width
* Set data width 32-bit: max resolution and CRC header
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
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2023-03-29 15:08:07 +03:00 |
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laurent-19
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1bef2bf304
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projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR
* Updated bd spi hierarchy, see library/spi_engine.tcl
* Enabled ext_clk for PWM to use 96 MHz spi clk
* Modified PWM channels used:
- ch1: ODR - 850 ns period, 130 ns high time
==> max fODR = 1.18 MHz
- ch0: trigger - 850 ns period, 30 phase shift
==> 10 ns between falling ODR rising DCLK
* Changed spi offload trigger signal:
- replaced edge detect,sync_bits IPs with PWM trigger
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
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2023-03-29 15:08:07 +03:00 |
sergiu arpadi
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4827e5eb18
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ad7134_fmc: Switch offload trigger to falling ODR
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2022-02-07 14:41:25 +02:00 |
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Sergiu Arpadi
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297bed6721
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ad7134_fmc: Change ODR signal to output
FPGA is now generating the ODR signal using axi_pwm_gen.
Both ADCs are now in slave mode.
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2022-02-07 14:41:25 +02:00 |
Stanca Pop
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12c474ba13
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ad7134: Change maximum data width from 24b to 32b
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2019-10-16 17:35:24 +03:00 |
Istvan Csomortani
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21ce53f765
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Revert "Move GTM projects to gtm_projects branch"
This reverts commit 171093eca4.
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2019-06-28 11:18:29 +03:00 |
Adrian Costina
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171093eca4
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Move GTM projects to gtm_projects branch
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2018-06-15 16:28:40 +03:00 |
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Istvan Csomortani
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53fa482837
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ad7134_fmc: Initial commit
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2018-04-11 15:09:54 +03:00 |