f7190dbbfd
adxcvr: Update Makefiles
2017-04-03 12:38:40 +03:00
fa5f81f6c6
axi_dacfifo: Fix clock for read address generation
2017-04-03 10:39:17 +03:00
7cb7bc111e
axi_dacfifo: Delete unused wires
2017-04-03 10:38:50 +03:00
14b4c4cf5f
axi_dacfifo: Define constraint for bypass
...
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
2017-04-03 10:38:28 +03:00
06605ed1e1
axi_dacfifo: Register the dac_valid signals
2017-04-03 10:38:09 +03:00
77081a6233
axi_dacfifo: Data from DMA is validated with dma_ready too
2017-04-03 10:37:45 +03:00
af3a4f5fc9
axi_dacfifo: axi_dvalid should come from dacfifo_rd module
2017-04-03 10:37:30 +03:00
b30041f7f3
axi_dacfifo: Redesign the bypass functionality
2017-04-03 10:37:08 +03:00
434d1ea52c
axi_dacfifo: Fix constraints
2017-04-03 10:36:46 +03:00
2f023437b4
adi_ip- remove adi_ip_constraints
2017-04-02 10:42:51 -04:00
d916697263
adi_ip- a little rearrangement
2017-04-01 09:04:35 -04:00
fd56b5a6d3
axi_ad9122: Update constraint files
2017-03-31 10:13:42 +03:00
c46989e4e8
Makefile: Update Makefiles for libraries
2017-03-30 18:33:22 +03:00
495d2f3056
axi_dmac: Propagate awlen/arlen width through the core
...
Depending on whether the core is configured for AXI4 or AXI3 mode the width
of the awlen/arlen signal is either 8 or 4 bit. At the moment this is only
considered in top-level module and all other modules use 8 bit internally.
This causes warnings about truncated signals in AXI3 mode, to resolve this
forward the width of the signal through the core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 17:19:38 +02:00
ebfed4b24b
ad_axi_ip_constr.xdc: Delete file
2017-03-30 16:16:02 +03:00
873fbfd6d7
library: Update scripts with new constraints
...
Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0
2017-03-30 16:16:02 +03:00
31a5c674f2
fmcomms2: Update constraints file paths
2017-03-30 16:16:02 +03:00
8ba6012b6b
restructure: Move xilinx specific constraints to /library/xilinx/common/
2017-03-30 16:16:02 +03:00
983e56d72c
ad9963: Remove localparams from module parameter list
...
Declaring local parameters in the module parameter list is not valid
verilog. For some reasons Vivado accepts it nevertheless so the code has
worked so far. But this is not true for other tools, so move the local
parameter definitions inside the module body.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 11:40:28 +02:00
e04793b6eb
m2k: standalone: Assign 0 to unused GPIO inputs
...
To avoid warnings from the tools assign 0 to the unused GPIO inputs.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 11:16:25 +02:00
8eb1dd0a8b
adrv9371x/altera- xilinx/chip-select consistency
2017-03-29 12:59:09 -04:00
1d448f0013
adi_ip: Set up SCOPE_TO_REF for xdc and save the core
2017-03-29 18:40:24 +03:00
ea7e93d27f
fmcomms2: Use the new constriants from 335fef0
2017-03-29 18:36:09 +03:00
335fef0f42
ad_axi_ip_constr: Split up this constraint file into separate files
...
For experimentation, to solve a constraint scoping issue, split up the
ad_axi_ip_constraint file into separate constraints file, in function
of there parent module.
2017-03-29 18:31:40 +03:00
24a7d8ea9d
m2k: Remove redundant s_axi_{aclk,aresetn} assignment
...
ad_cpu_interconnect will make sure to connect the clock and the reset of
the AXI interface. Remove the redundant manual assignments.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-28 11:14:48 +02:00
deb8635854
adrv9371x/altera- gpio equivalency fix
2017-03-27 16:37:55 -04:00
8f1564a9c4
adrv9371x/a10gx- gpio matching
2017-03-27 13:51:45 -04:00
2419b3626b
ad9684- fix sdc typo
2017-03-23 12:49:44 -04:00
ae0f4672b2
daq1/a10gx- fix project to compile
2017-03-23 09:46:40 -04:00
cc6bf53d98
adrv9371x/a10soc- altera reset synchronizer false path?
2017-03-23 09:46:40 -04:00
968d94603e
fmcjesdadc1: Update xcvr configuration to the default one used for this board
2017-03-23 11:31:00 +02:00
4a275302a0
a5soc- add ddr3 location assignments
2017-03-22 10:12:34 -04:00
7e87ecae22
altera/a10gx- daq1/fmcomms2 fix typos
2017-03-22 09:48:02 -04:00
b3f06af77a
altera srf files do not work
2017-03-22 09:25:50 -04:00
66a5d44a18
a5gte- add constraints for tq
2017-03-21 10:53:31 -04:00
2e22ce3b62
a10gx- ignore preliminary timing model warnings
2017-03-21 10:52:28 -04:00
d84e34fe5f
arradio/c5soc- reset false path for vga dma
2017-03-21 10:15:38 -04:00
8063ba2b66
make updates
2017-03-20 16:05:18 -04:00
c7351f3ce3
arradio/c5soc- remove qsys files
2017-03-20 15:56:07 -04:00
589e6b53d8
arradio/c5soc- qsys-script flow
2017-03-20 15:42:33 -04:00
b39fecadd9
altera- ignore preliminary timing messages
2017-03-20 12:48:53 -04:00
7dfa8c599f
arradio/c5soc- updated to new framework/16.0
2017-03-20 12:15:18 -04:00
12f44ccbcc
arradio/c5soc- critical warnings fix
2017-03-20 12:14:21 -04:00
c277b39796
arradio/c5soc- critical warnings fix
2017-03-20 12:14:13 -04:00
9b6dd27c23
ad9361- delay initialization
2017-03-15 12:06:59 -04:00
09bcecb6ed
m2k: Simplify DMA connection to HP1
2017-03-15 15:11:30 +02:00
cd0701513a
axi_logic_analyzer: Added an additional delay to the trigger, to be similar with the analog path
2017-03-14 18:00:42 +02:00
3c7f73a880
axi_dmac: Fix dummy port enablement dependency
...
It seems that in the latest version a constant of "0" is no longer a valid
enablement dependency and "false" has be used instead.
Not setting the enablement dependency correctly results in the AXI port to
be assumed to be read-write rather than just read or write. This will
generate unnecessary logic for example in interconnects to which the DMA
controller is connected.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-14 16:03:25 +01:00
d7edd71aef
axi_logic_analyzer: Triggering changes on valid data
2017-03-14 15:25:00 +02:00
2a9b3cea09
m2k: Changed the way DMAs connect to the PS7 DDR, to optimize resources use
2017-03-14 13:57:50 +02:00
Istvan Csomortani
Rejeesh Kutty
Lars-Peter Clausen
Istvan Csomortani
Adrian Costina