bf88527119
library: jesd204: jesd204_up_common: Fix indention
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
2e8be3d7a6
daq2: Provide DAC lane map
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Provide the correct lane mapping for the DAQ2 DAC lanes which do not follow
a 1-to-1 mapping between physical and logical lanes due to PCB layout
constraints.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
4bf5990451
adi_board.tcl: ad_xcvrcon: Add lane mapping support
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Add a parameter to the ad_xcvrcon function that allows to provide a mapping
between logical and physical lanes. By default if no lane map is provided
the logial and physical lanes are mapped 1-to-1. If a lane map is provided
logical lane $n is mapped onto physical lane $lane_map[$n].
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
9f954303ac
up_clock_mon: Fix stopped clock detection logic
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A broken version of the stopped clock detection logic was merged by
accident. Fix it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
f415b4f973
axi_ad5766: Delete unused interface definition
2017-06-20 11:55:10 +01:00
871855c9ec
axi_logic_analyzer: Fix delayed trigger assertion condition
2017-06-19 10:58:22 +03:00
d840baee28
util_clkdiv: Register output port as a clock ( #33 )
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If the output pin is not defined as a clock, some of the Vivado IPI
propagation TCL will error out.
Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
2017-06-19 07:52:43 +01:00
25a9949899
util_clkdiv: Register output port as a clock ( #33 )
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If the output pin is not defined as a clock, some of the Vivado IPI
propagation TCL will error out.
Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
2017-06-19 07:40:53 +01:00
dc94dd3ea7
jesd204- apply constraints after top
2017-06-16 15:30:18 -04:00
513f6ae18a
adi_ip.tcl- general rule- order independent constraints
2017-06-16 13:51:35 -04:00
56867b362e
daq3- updated to 12.5G
2017-06-16 09:02:26 -04:00
3fb5408acc
fmcjesdadc1/a10gx- fix sysref, lvds io and such
2017-06-15 13:57:21 -04:00
6ec9eab7b9
fmcjesdadc1/a10soc- fix sysref, lvds io and such
2017-06-15 13:57:21 -04:00
ef290ef484
hdlmake.pl updates
2017-06-15 11:42:44 -04:00
e33e6a84f4
a5gt/a5soc - removed
2017-06-15 11:41:28 -04:00
a23fb793a0
a5gt/a5soc - removed
2017-06-15 11:40:58 -04:00
9e2d55ed07
adi_ip_alt: allow composition only parameter settings
2017-06-15 11:36:39 -04:00
9464f342cf
avl_adxcvr: remove arria v support
2017-06-15 11:36:14 -04:00
2649458b6d
hdlmake.pl updates
2017-06-15 10:21:57 -04:00
fd0c7f1b1c
usdrx1/a10gx- updated to a10gx
2017-06-15 10:21:57 -04:00
0311ed411c
usdrx1/a10gx- added
2017-06-15 10:21:57 -04:00
7ac083b932
fmcjesdadc1/a10soc- sysref fixes
2017-06-15 10:15:59 -04:00
004aee930b
fmcjesdadc1/a10gx- fix sysref, gpio connections
2017-06-14 14:40:23 -04:00
dba419239b
hdlmake.pl updates
2017-06-14 10:41:14 -04:00
3299d244fe
fmcjesdadc1: a10gx/a10soc
2017-06-14 10:39:57 -04:00
38c708d4d0
fmcjesdadc1: a10gx/a10soc
2017-06-14 10:39:38 -04:00
105b9e7114
fmcadc5: Delete clock and reset duplicate connection
2017-06-14 11:33:11 +03:00
051c1d6644
fmcjesdadc1: a10soc
2017-06-13 15:00:22 -04:00
c1bc1259a7
fmcjesdadc1: a10gx
2017-06-13 12:39:45 -04:00
3f3ea5f99a
hdlmake.pl- updates
2017-06-13 09:55:08 -04:00
ffb6cd4b0b
scripts- add a5soc device
2017-06-13 09:54:01 -04:00
ff646b0cfc
common/a5soc- alt 16.1 updates
2017-06-13 09:54:01 -04:00
0eacde9158
fmcjesdadc1/a5soc- alt 16.1 updates
2017-06-13 09:54:01 -04:00
2fc5d08c0b
axi_gpreg: Fixed constraints
2017-06-13 14:04:43 +03:00
6decba3c3b
hdlmake.pl updates
2017-06-09 16:23:17 -04:00
173837f5b2
altera- altera ip interfaces has no consistency
2017-06-09 16:21:44 -04:00
74f9a99655
fmcjesdadc1/a5gt- altera 16.1 updates
2017-06-09 16:20:49 -04:00
2e17e67627
common/a5gt- altera 16.1 updates
2017-06-09 16:20:15 -04:00
688758e6c6
scripts/adi_project_alt- add a5soc, a5gt
2017-06-09 16:19:29 -04:00
227bd3edfe
alt_ifconv-- qsys workaround
2017-06-09 16:17:34 -04:00
033737d6bf
adi_board.tcl: reset xilinx ip second commit
2017-06-09 19:16:19 +03:00
b14c3fb00d
Revert "adrv9371x- reset jesd ip using cpu clock"
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This reverts commit 9feeb72631
2017-06-09 19:12:36 +03:00
ca536d50ac
altera 16.1 c5soc updates
2017-06-08 15:03:03 -04:00
f3af192f30
altera 16.1 arradio updates
2017-06-08 15:02:46 -04:00
ca20309166
adi_project_alt: add c5soc
2017-06-08 15:02:24 -04:00
034aa7c1ee
altera 16.1- recommends using fpll for dedicated low skew clock routing
2017-06-08 10:50:52 -04:00
9feeb72631
adrv9371x- reset jesd ip using cpu clock
2017-06-08 10:49:37 -04:00
0b450a3dd7
adi_board.tcl: reset xilinx ip using cpu clock
2017-06-08 10:16:43 -04:00
3f2c885189
axi_logic_analyzer: Update triggering delay mechanism
2017-06-08 12:01:49 +03:00
256a685004
axi_adc_trigger: Update triggering delay mechanism
2017-06-08 12:00:27 +03:00
Lars-Peter Clausen
Istvan Csomortani
Adrian Costina
Matthew Fornero
Rejeesh Kutty
AndreiGrozav