The PLL frequency must be half of the lane rate and the core clock rate
must be lane rate divided by 40. There is no other option, otherwise things
wont work.
Instead of having to manually specify PLL and core clock frequency derive
them in the transceiver script. This reduces the risk of accidental
misconfiguration.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The clock bridge expects the clock rate to be specified in Hz, but
$m_coreclk_frequency is in MHz. Do the appropriate conversion.
Nothing seems to rely on the clock bridge reporting the correct frequency
at the moment, so this is only a cosmetic change.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
While things seem to work fine with only specifying the the IO standard for
the positive side of differential signals Quartus will issue a warning
about incomplete constraints if the IO standard is not specified for the
the neagtive side as well. To avoid these warnings add the missing
constraints.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Fix a copy and paste error and specify the IO_STANDARD for all gpio_bd_i
rather than twice for half of them.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The ad_pps_receiver is instantiated at the top of core.
The rcounter is placed into adc/dac_common registers space, at the
address 0x30 (word aligned).
The interrupt mask is placed into adc/dac_common, at the address 0x04
(word aligned). Because the core has an instance of both modules, the
interrupt masks are OR-ed together.
Add a module to receive 1PPS signal from a GPS module. The module has a
free running counter, which runs on the device's interface clock. The
counter value is latched into a register each time when a 1PPS arrives.
An interrupt signal is also generated in every 1PPS.
Add a check to RX register map to confirm that the ILAS memory registers
return the correct values after the ILAS data has been received.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Both the sys_hps.f2sdram_clock and the sys_dma_clk.clk signal are in the
same clock domain. They are both driven by the same clock. And even though
qsys is capable of detecting this it seems qsys interconnect is not able to
infer this and inserts a extra clock domain crossing bridge between the DMA
and the HPS AXI system memory interface.
To avoid this connect the sys_dma_clk.clk to the sys_hps.f2sdram_clock so
that all components are driven by the same qsys clock signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The MSB of the d_count signal is used as a overflow marker to stop the
counter from incrementing in the monitored clock domain. It is not exported
through the register map and truncated when assigned to the up_d_count
signal.
Make the truncation explicit to make it clear that this is not a mistake
and to avoid warnings about implicit truncation.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The generic Altera clock monitor constraints expect the instance to be
called i_clock_mon. Adjust the code accordingly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In this particular case the behaviour is the same with non-blocking and
blocking assignments, but that could change if the code is modified in the
future. To avoid any potentially issue due to this consistently use
non-blocking assignments.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Rejeesh Kutty
AndreiGrozav
Adrian Costina
Lars-Peter Clausen
Istvan Csomortani
Nick Pillitteri