a06c74edc7
fmcjesdadc1: Change rx_div_clk to 125MHz
2019-11-20 10:50:18 +02:00
9260979b15
adrv9364: Added sysid to all projects
2019-11-20 10:43:54 +02:00
570dae7df6
adrv9361: Added sysid to all projects
2019-11-20 10:43:54 +02:00
24b5de4438
sysid: Specified clock interface for input clk
2019-11-20 10:43:54 +02:00
dfe3258a4f
adrv9009zu11eg: Add axi_sysid
2019-11-19 10:29:57 +02:00
81d3a9eb66
adrv9009zu11eg: Reduce SPI Clock speed to meet timing
2019-11-19 10:29:57 +02:00
4b380fe640
ad7768-1evb: Add coraz7s support
2019-11-15 14:35:00 +02:00
40d839df5f
coraz7s: Initial commit
2019-11-15 14:35:00 +02:00
514aadb54e
m2k: Use dac trigger
2019-11-15 12:23:01 +00:00
af2f243b02
axi_dac_interpolate: Add dac trigger feature
2019-11-15 12:23:01 +00:00
a589a2c7eb
adrv9009_zu11eg_som: Change design partitioning
...
Create a structure similar with ADRV936x projects
2019-11-14 15:25:23 +02:00
39d19ef401
util_adxcvr: Add additional parameters allowing for GTH4 RX 15Gbps rates
2019-11-11 14:46:09 +02:00
eab1e86544
adrv9364z7020: Rename *box project to *packrf
2019-10-29 16:07:08 +02:00
de324526e3
adrv9361z7035: Rename *box project to *packrf
2019-10-29 16:07:08 +02:00
64f5a99c63
axi_adc_trigger: Add and 1 extra delay
...
The extra delay was added on the trigger and data paths to compensate
for the logic analyzer changes.
The extra delay will be also seen on the m2k daisy chain. The
delay between devices will be increased from 3 to 4 samples delay.
2019-10-28 13:13:10 +00:00
10c99562cf
axi_logic_analyzer: Add extra reg pipe to avoid latch
2019-10-28 13:13:10 +00:00
6af5d3c358
axi_logic_analyzer: Improve external trigger
...
Fix external trigger for low sampling rates.
Because the external trigger can be a short pulse at high decimation rates
there is a high chance that the pulse will be missed.
2019-10-28 13:13:10 +00:00
5dc2ab9fe7
spi_engine/execution: dynamic length bugfix
...
ip can now send multiple words per transfer with dynamic data length
2019-10-28 12:00:23 +02:00
2ea8838f6a
spi_engine/execution: wire/reg must be defined before usage
...
xsim does not like if a register or wire is used before their
definition. Make sure the every register and wire is defined before it's
used the first time.
2019-10-28 12:00:23 +02:00
fba7cac0c6
ad7768-1evb: Remove ADC2, update spi engine framework
...
The second ADC was removed from the project, as the EV-AD7768-1FMCZ evaluation
board contains only one ADC. Therefore, all the IPs related to the
second ADC have been removed, too.
The data width supported by the spi IPs has been changed from 8 bits to
32 bits, therefore the axis_upscaler(util_axis_upscale_v1_0) and the
m_axis_samples_24(AXI4-Stream Data Width Converter) are no more necessary,
so they have been removed from the design.
The 24 bits width data transfer between the s_axis of axi_ad77681_dma
(AXI DMA Controller) and the offload_sdi of the spi_engine_offload is now made
directly.
2019-10-28 12:00:23 +02:00
4941d89fff
cn0506_mii: Add support on a10soc
2019-10-18 19:09:04 +03:00
fbb3a154ff
cn0506_mii: Add support on zcu102
2019-10-18 19:09:04 +03:00
3cb2392711
cn0506_mii: Add support on zc706
2019-10-18 19:09:04 +03:00
e98951d282
cn0506_mii: Add support on zed
2019-10-18 19:09:04 +03:00
8202c0025c
cn0506_mii: Common design initial commit
2019-10-18 19:09:04 +03:00
9323f4193c
m2k: Clean old interrupt connection style
2019-10-18 18:28:01 +03:00
a4547a32b6
pluto: Clean old interrupt connections style
2019-10-18 18:28:01 +03:00
fd4d32c408
projects/scripts/*xilinx*: Generate report utilization extra files
...
Add commands to generate one extra file with resource utilization, in CSV format.
New commands executes only if ADI_GENERATE_UTILIZATION env variable is set.
2019-10-18 13:42:34 +03:00
5a4726b356
adrv9364z7020: Fix interrupt concatenation
2019-10-17 15:09:48 +03:00
f0f314f24b
adrv9361z7035: Fix interrupt concatenation
...
None functional change, main goal is to increase consistancy in our
code base.
2019-10-17 15:09:48 +03:00
80333573c7
ad_fmclidar1_ebz/zcu102: Fix SYSREF input delay constraint
...
Add one clock cycle input delay for the SYSREF input,
to compensate the high propegation delay of device_clk_BUFG.
2019-10-17 09:59:23 +03:00
03bec4b49c
ad_fmclidar1_ebz: Interchange SYSREF and DEV_CLK ports location
...
In ZCU102 LA01_CC_P|N are connected to regional clock, but in order to
receive a device clock properly we have to use pin which is connected
to a global clock buffer. Luckily SYSREF is connected to global clock
pin; swap to port to receive the device clock correctly.
Also, swap the ports in both ZC706 and A10SOC carriers.
2019-10-17 09:59:23 +03:00
2cabf8d224
ad_fmclidar1_ebz: Move afe_iic definition to system_bd.tcl
...
In order to prevent platform specific variable usage in the common tcl
script, move the AFE I2C interface definition to system_bd.tcl
2019-10-17 09:59:23 +03:00
b3e1cd2a15
ad_fmclidar1_ebz: Add support for ZCU102
2019-10-17 09:59:23 +03:00
3084a5d9aa
ad_fmclidar1_ebz/a10soc: Fix the comment about the carrier re-work
...
The project is using the FMCA connector of the board. Make sure that all
the carrier re-work is related to the FMCA connector.
2019-10-17 09:58:52 +03:00
12c474ba13
ad7134: Change maximum data width from 24b to 32b
2019-10-16 17:35:24 +03:00
e7636f0380
axi_laser_driver: Define up_pulse_s wire in regmap
2019-10-16 15:18:43 +03:00
5bcaf05355
ad_ss_444to422: localparam can not be used in port definition
2019-10-16 15:18:29 +03:00
b62aab985d
ad_csc_RGB2CrYCb: localparam can not be used in port definition
2019-10-16 15:18:29 +03:00
1b2405a454
ad_csc_CrYCb2RGB: localparam can not be used in port definition
2019-10-16 15:18:29 +03:00
3c46cc9347
dac_fmc_ebz: Add project info to sys_id
...
Add project device and mode info to sys_id custom string
2019-10-15 17:08:53 +03:00
58b846faae
dac_fmc_ebz: Add build time config option
2019-10-15 17:08:53 +03:00
e22016de4c
adrv9371/daq2/daq3:kcu105: patch GTH3 CPLL parameters
...
Update GTH3 parameters according to a 10Gbps link from the Transceiver
Wizard.
2019-10-08 10:38:46 +03:00
fd74c270c5
adi_ip_xilinx: Add constraint files to constrs_1 fileset
2019-10-03 18:04:34 +03:00
8895b08eb1
adrv9009_zu11eg_som: i2s mclk fix
...
mclk now generated by ps not axi clkgen ip. ADAU1761 expects a free
running clock and the i2s driver was switching the axi clkgen ip off
which was causing issues.
2019-10-03 17:30:57 +03:00
5b79df1aa8
sys_id: version fix
2019-10-03 17:30:18 +03:00
2344778dd8
ad_fmclidar1_ebz/a10soc: Initial commit
...
Add initial support for Arria 10 SOC carrier.
2019-10-02 15:32:17 +03:00
23d29e7a15
a10soc_system_qsys: sys_dma_clk clock_source inherit its clock frequency from its source
2019-10-02 15:32:17 +03:00
97d4a14e2b
util_cpack2_hw.tcl: Define allowed ranges for NUM_OF_CHANNELS
...
The number of channels must be round up to the closest next power of
two.
2019-10-02 15:32:17 +03:00
acba490c2e
ad_ip_jesd204_tpl_adc: BITS_PER_SAMPLE is a HDL parameter
2019-10-02 15:32:17 +03:00
Stanca Pop
Sergiu Arpadi
Adrian Costina
AndreiGrozav
Istvan Csomortani
Stefan Raus
Laszlo Nagy