Commit Graph

3059 Commits (93f46ef6e34b3afb220aa32b9ce174ddcfab92e7)

Author SHA1 Message Date
Laszlo Nagy dd4c8d6807 adrv9001/zcu102: Add debug header 2021-01-26 15:22:41 +02:00
Laszlo Nagy 728904af09 adrv9001/zcu102: Run postRoutePhysOpt to close Rx1 to Rx2 path timing 2021-01-26 15:22:41 +02:00
Laszlo Nagy bae7e48c50 adrv9001/common: Run DMAs @ 100MHz 2021-01-26 15:22:41 +02:00
Sergiu Arpadi f68c222489 cn0501/coraz7s: Fix sysid 2021-01-22 15:40:37 +02:00
Laszlo Nagy bb44e5399f adrv9001/zed: Connect TDD sync to PMOD JA1 2021-01-20 13:00:01 +02:00
Laszlo Nagy 3918d43cd1 adrv9001/zcu102: Add TDD sync to PMOD0 J55.1 2021-01-20 13:00:01 +02:00
Laszlo Nagy fe9f72db9c adrv9001/common: Export TDD mode signal 2021-01-20 13:00:01 +02:00
Laszlo Nagy 18b2a8b0a7 adrv9001/zed: Add TDD support 2021-01-20 13:00:01 +02:00
Laszlo Nagy 0c2745361b adrv9001/zcu102: Add TDD support 2021-01-20 13:00:01 +02:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
Sergiu Arpadi da61515d41 ad40xx: Fix bd.tcl script 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
Laszlo Nagy da9828a63e ad9081:zcu102: Expose parameters to environment
Allow setting project parameters from the environment.
2021-01-19 17:10:08 +02:00
Istvan Csomortani 235fb4859a usrpe31x: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00
Istvan Csomortani f1421c91ee sidekiqz2: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00
Istvan Csomortani f68393ecb9 adrv936x: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00
Istvan Csomortani 3e237459e3 pluto: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00
Istvan Csomortani d9639db991 m2k: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00
Istvan Csomortani e41ba7f6f5 adrv9009zu11eg: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00
Istvan Csomortani 9ec3408c79 adi_project_xilinx: Fix the adi_project process
In most of the standalone projects the generic project creation flow is not followed. The project's device
is defined manualy. This fix makes sure that those projects still builds without an issue.

NOTE: In these case we should use adi_project_create directly in system_project.tcl.
2021-01-15 15:26:43 +02:00
Sergiu Arpadi b9ac8df503 project-xilinx.mk: Add *.hbs to clean list 2021-01-15 13:50:53 +02:00
Sergiu Arpadi 067b57d404 vc707: Fix mdio intf 2021-01-15 13:50:53 +02:00
Sergiu Arpadi c54552d823 adi_project_xilinx: Add env var
add ADI_DISABLE_MESSAGE_SUPPRESION which disables
adi_xilinx_msg.tcl

projects/scripts/adi_project_xilinx.tcl
2021-01-15 13:50:53 +02:00
Sergiu Arpadi ead4513ad6 adi_xilinx_msg: Downgrade Synth 8-2490 2021-01-15 13:50:53 +02:00
Arpadi 51b5e4f58b tcl: Change Vivado version to 2020.1
handoff is now exported as .xsa
2021-01-15 13:50:53 +02:00
Adrian Costina fbb2a0e1a0 de10nano: Add hps_conv_usb_n signal to stabilize UART lines
Without defining this signal, the UART lines receive garbage data
when no cable is connected to the J4 USB UART port.
The GPIO9 is enabled in the reference base design along with the
4MA CURRENT_STRENGTH constraint on the UART pins
2021-01-13 15:36:45 +02:00
Istvan Csomortani dee108ba22 fmcomms8/intel: Fix fPLL configuration
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.

The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.

Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
Istvan Csomortani 85f5dc8230 ad9371x/intel: Fix fPLL configuration
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.

The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.

Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
Istvan Csomortani d539a8119c adrv9009/intel: Fix fPLL configuration
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.

The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.

Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
aholtzma bab3426f91 scripts: allow directly specifying a device when creating a project
Add a layer under adi_project that allows you to directly specify a device/board combination without determining it from the project name.
2021-01-12 14:13:07 +02:00
Istvan Csomortani b989ba36d1 axi_spi_engine: Fix util_axis_fifo instance related issues 2021-01-08 12:29:26 +02:00
sergiu arpadi 5c87e5b1a7 cn0501: Initial commit for Coraz7s 2020-12-18 14:05:56 +02:00
Sergiu Arpadi 71009e74ff ad7768_if: Remove buffers, add parallel data path 2020-12-15 15:16:14 +02:00
AndreiGrozav fa67eb5532 adv7513_de10nano: Fix gpio_bd assignments 2020-12-08 14:38:04 +02:00
AndreiGrozav e331abedc6 common/de10nano: Cosmetic updates only 2020-12-08 14:38:04 +02:00
AndreiGrozav 8d378c56bf common/de10nano: Full HD 60 FPS support
-change the video memory interfacing from f2h_axi_slave to
f2h_sdram0
- add f2h_sdram1 port as the default interface for converter DMA
- set as default the full HD resolution at 60 FPS (pixel clock 148.5MHz)
- use a second 200MHz(198MHz) clock from the pixel_clk_pll, as DMA source
to destination clock.
2020-12-08 14:38:04 +02:00
Laszlo Nagy 3dd370a27c ad9081_fmca_ebz: enable xbar in DAC TPL 2020-11-27 09:45:11 +02:00
Laszlo Nagy ad755788a0 ad9081_fmca_ebz/zc706: Initial version
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2020-11-12 15:46:27 +02:00
Laszlo Nagy e9f319e3d7 ad9081_fmca_ebz: HP0 is already initialized in ZC706
On carriers like ZC706 the HP0 interconnect is in already in use so it must
not be initialized here.
2020-11-12 15:46:27 +02:00
Adrian Costina b080b52a14 daq3:zcu102: Connect overflow pins for the AD9680 TPL 2020-11-11 14:24:02 +02:00
Istvan Csomortani 2799777657 adrv9009zu11eg/adrv2crr_fmc: Fix hmc7044_car_gpio connections 2020-11-11 07:07:29 -05:00
Adrian Costina ecd880d44c adrv9009zu11eg:fmcomms8: Fix SPI timing constraint 2020-11-05 17:42:41 +02:00
stefan.raus 685ca91f19 ad_fmclidar1_ebz/a10soc: Fix a typo
Fixing a typo in projects/ad_fmclidar1_ebz/a10soc/system_top.v.
2020-11-05 12:53:50 +02:00
aholtzma 2ff5420630 Update system_top.v
Add a comment that the spi CS decoding is tied to a setting in the device tree.
2020-11-02 16:59:08 +02:00
IMoldovan 78b2ae02a1 ad9434_fmc,ad9467_fmc,fmcadc5: Update projects to use ad_iobuf, not IOBUF 2020-11-02 16:13:35 +02:00
Adrian Costina a3a610728c intel: Update projects to use ad_iobuf instead of ALT_IOBUF 2020-11-02 16:13:35 +02:00
Adrian Costina ae7ec82334 adrv9009zu11eg: Update spi module to use generic verilog 2020-11-02 16:13:35 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
AndreiGrozav 912e09ad18 m2k: Add DAC last sample connections 2020-11-02 15:50:12 +02:00
Istvan Csomortani d676cfd64f adv7513/de10nano: Define the USB clock 2020-10-30 10:55:01 +02:00