Commit Graph

15 Commits (93f46ef6e34b3afb220aa32b9ce174ddcfab92e7)

Author SHA1 Message Date
AndreiGrozav 4766d01915 m2k: Update constraints 2020-08-13 07:01:19 +03:00
AndreiGrozav 9f112640f3 m2k: Change constraint to match the new LA path 2019-09-13 11:55:11 +03:00
AndreiGrozav 6f540b0ef2 m2k: Add cascading support
-remove util_extract
-instrument triggering logic_analyzer <-> adc_trigger using dedicated latency paths
-move logic_analyzer on adc clock domain (100MHz -> 100MHz)
2019-08-22 18:06:10 +03:00
Laszlo Nagy 0261eade0c zynq:all: fix SPI clock constraint
According to data sheets the EMIO SPI controller maximum frequency is
just 25MHz. Constrain the SPI clock accordingly.
2019-08-09 16:39:56 +03:00
AndreiGrozav 0a3a99bf83 m2k: Define SPI clock constraint 2019-06-21 09:53:14 +03:00
Adrian Costina 07e52b4566 m2k: Connect logic_analyzer path to clk_out instead of clk
- this allows for the clock switching to be done inside axi_logic_analyzer core
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen c9f863f189 m2k: standalone: Set static switching activity for the reset signals
The global reset signals are only asserted for a short moment during system
startup and deasserted during normal operation, which is the case we care
about for power analysis. Giving them a static switching probability
indicating that they are always de-asserted will yield better results for
power analysis.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen c1ba57f808 m2k: Rework clocking domains
At the moment the register map fabric and DMA system memory side are
clocked by the 100MHz sys_cpu_clk. While this works fine that is a lot
faster than the clock has to run. There are only a few 100 register map
accesses per seconds at most and they are not on timing critical paths. The
penalty from clocking them at a lower rate is negligible for the overall
system performance.

The maximum clock rate for the DMAs is determined by the throughput
requirements. This is 200 Mbytes/s for the logic analyzer, pattern
generator and each of the DAC DMAs and 400 Mbytes/s for the ADC DMA.

The DMA datapath width is 64-bit so the required clock rates are 25MHz and
50MHz respectively. Some headroom is required to accommodate for occasional
bubble cycles on the data bus and the difference in reference clocks for
the converter and processing system.

The sys_cpu_clk is reduced to 27.8MHz which is fast enough for all but the
ADC DMA. For the ADC DMA a new clock domain running at 55.6 MHz is
introduced.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 2eaf931e07 m2k: Replace logic analyzer MMCM
The MMCM generating the logic analyzer clock unfortunately consumes a
disproportionately large amount of power compared to the rest of the
design.

Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs.
The IO PLL is running anyway so the power requirement is much lower.

For the time being this means we loose the ability to source the clock from
an external pin. But that feature is not supported by software at the
moment anyway. We'll bring it eventually when required.

This changes reduces power consumption by roughly 100mW.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Adrian Costina 6a49aefb6c m2k: Updated project to use new tx path with serdes 2017-04-18 12:17:39 +02:00
Adrian Costina eda585f0e4 m2k: Connected data[0] and trigger[0] pins to the logic analyzer clock generator input 2 2017-02-27 14:16:32 +02:00
Adrian Costina e215a091b2 m2k: standalone, added explicit fclk_clk0 and fclk_clk1 constraints 2017-02-13 12:02:59 +02:00
Adrian Costina 0d0c3e99fd m2k: Added I2C pull-ul, removed SLEW constraints 2017-02-02 12:35:46 +02:00
Adrian Costina cfff70d358 M2K: Update standalone project
- configured PS7 similar to pluto. Added specific constraints instead of default PS7
- moved ad9963_resetn and en_power_analog to gpio[0] and gpio[1]
2017-02-01 14:27:11 +02:00
Adrian Costina b14d740f87 M2K: initial commit 2017-01-31 16:43:40 +02:00