Adrian Costina
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59dda01419
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m2k: Disabled DDS cores for the generic project
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2017-02-28 10:10:28 +02:00 |
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Adrian Costina
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545e458997
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m2k: Standalone, ignored critical warning for contraints that should only be applied at the implementation stage
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2017-02-27 14:17:29 +02:00 |
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Adrian Costina
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eda585f0e4
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m2k: Connected data[0] and trigger[0] pins to the logic analyzer clock generator input 2
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2017-02-27 14:16:32 +02:00 |
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Adrian Costina
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908da60ab6
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m2k: zed, changed constraints so they are the same with the ZED default configuration
- the voltage can be physically changed between 1.8V, 2.5V and 3.3V
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2017-02-27 14:13:34 +02:00 |
Rejeesh Kutty
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c598e84258
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remove processing order (no clock def dependency)
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2017-02-22 16:02:08 -05:00 |
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Adrian Costina
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e215a091b2
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m2k: standalone, added explicit fclk_clk0 and fclk_clk1 constraints
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2017-02-13 12:02:59 +02:00 |
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Adrian Costina
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4e62fb0ef3
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m2k: Add reset circuitry on the logic_analyzer clock domain
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2017-02-13 12:02:11 +02:00 |
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Adrian Costina
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6aadb49e80
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m2k: Remove use board flow from the standalone version
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2017-02-02 12:58:58 +02:00 |
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Adrian Costina
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0d0c3e99fd
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m2k: Added I2C pull-ul, removed SLEW constraints
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2017-02-02 12:35:46 +02:00 |
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Adrian Costina
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5155b3f46d
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m2k: Fix gpio buswidth
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2017-02-01 17:43:01 +02:00 |
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Adrian Costina
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cfff70d358
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M2K: Update standalone project
- configured PS7 similar to pluto. Added specific constraints instead of default PS7
- moved ad9963_resetn and en_power_analog to gpio[0] and gpio[1]
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2017-02-01 14:27:11 +02:00 |
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Adrian Costina
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6bdd853b88
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m2k: Updated PS7 configuration
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2017-01-31 23:08:53 +02:00 |
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Adrian Costina
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b14d740f87
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M2K: initial commit
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2017-01-31 16:43:40 +02:00 |