2b274f945f
ad9081_fmca_ebz: Reset cpack with Rx data offload
2022-08-01 12:47:26 +03:00
961ebe0cc2
projects: Update .v files according to guideline
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Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
b3d231e569
ad9081_fmca_ebz/zc706: Make second sync CMOS and GPIO controllable
2022-05-26 09:13:05 +03:00
97b92565b2
Makefile: Replace util_fifo2axi_bridge with util_hbm
2022-04-28 14:31:32 +03:00
77f3e5155b
ad9081_fmca_ebz: Fix signal length parameter
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Corrected the length parameter for the rx_data input.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-08 14:29:48 +02:00
9295218a64
projects/ad9081_fmca_ebz: Updated makefiles
2021-10-05 16:56:57 +03:00
51b643b978
Makefile: Fix misc makefiles from projects and library
2021-10-05 14:24:48 +03:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
e9e278c898
ad9081_fmca_ebz: Remove bypass gpio
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
0d9e38bdbe
ad9081_fmca_ebz: Update path to common block design
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Use absolute paths so ad9082 wrapper project can include the
system_bd.tcl instead of duplicating code.
2021-05-14 15:39:40 +03:00
680d28476c
ad9081_fmca_ebz: Add LANE_RATE param to all projects
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The block design expects a lane rate to be set in the system project.
2021-05-14 15:39:40 +03:00
d0f8a81b2f
ad9081_fmca_ebz: Np 12 support
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204B functional
204C functional
2021-02-05 15:24:15 +02:00
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
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Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
ad755788a0
ad9081_fmca_ebz/zc706: Initial version
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M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2020-11-12 15:46:27 +02:00
Laszlo Nagy
Iulia Moldovan
Dan Hotoleanu
Filip Gherman
Adrian Costina
David Winter
Sergiu Arpadi