0c0617d49e
libraries: Update modules according to guideline
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* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
076e81a17c
library: Add link to wiki for IPs
2021-10-25 10:44:53 +03:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
4a772265a9
Update Quartus Prime version from 19.3.0 to 20.1.0
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adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
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Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
37254358dd
makefile: Regenerate make files
2020-10-20 12:51:10 +03:00
4a28a4e856
sysid_intel: Added hw.tcl for sysid IP cores
2020-09-11 15:46:06 +03:00
907d6fcbd9
sysid_intel: Fixed axi_sysid module name
2020-05-18 14:19:42 +03:00
5b79df1aa8
sys_id: version fix
2019-10-03 17:30:18 +03:00
4fe5f007cb
system_id: added axi_sysid ip core and tcl
2019-08-06 16:53:11 +03:00
Iulia Moldovan
LIacob106
Adrian Costina
stefan.raus
sergiu arpadi
Istvan Csomortani