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10 Commits (922ea7fb34d97a4443a48068f18ed75292ca4213)

Author SHA1 Message Date
Adrian Costina f79a152958 Makefiles: updated all makefiles adding clean functionality 2015-04-03 11:57:54 +03:00
Rejeesh Kutty 48e8945ac1 makefile: added 2015-04-01 16:29:29 -04:00
Adrian Costina dbcf8389b3 fmcomms1: Updated zed project to the latest framework 2015-03-27 15:37:50 +02:00
Lars-Peter Clausen abde4048e0 fmcomms1: Add extra AXI slice on ADC DMA path 
Add a extra AXI slice on the ADC DMA data path to the HP interconnect to
improve the timing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-02-20 16:43:45 +01:00
Adrian Costina adcd16d033 fmcomms1: Updated zed project 
- fixed timing constraints
- used ad_iobuf
- updated interrupt system to latest implementation
 2014-11-17 18:31:24 +02:00
Adrian Costina 3c25c1171d fmcomms1: Fixed missing sample issue on ZC706. Added modifications for all other platforms 2014-09-26 10:28:07 -04:00
Adrian Costina ad5ef35b48 fmcomms1: modified *_bd.tcl files formatting 2014-03-26 12:05:42 +02:00
Adrian Costina ab8627e669 fmcomms1: Changed ILA data capture and sys constraints 
The ILA can not work at 250MHz on ZED/ZC702. Because of this, the data
path was modified from 28bits@250MHz to 56bits@125MHz, by using a FIFO.
The ZED/ZC702 max BUFG frequency is 464MHz, which corresponds to a 2.16
period so the constraints were modified accordingly.
 2014-03-17 15:50:01 +02:00
Adrian Costina 92aaf0bd51 FMCOMMS1: Updated projects and axi_ad9643 core 
ZC702: Removed invalid address segments. Changed the constraints
for adc_clk to minimum possible value in order to meet timing.

ZED: Change the constraints for adc_clk to minimum possible value, in
order to meet timing

AXI_AD9643: Corrected the number of bits in the adc_mon_data bus
 2014-03-12 16:23:41 +02:00
Rejeesh Kutty f8ab734918 projects/fmcomms1: added 2014-03-11 12:16:25 -04:00