Commit Graph

11 Commits (912e09ad188bec0985ee512b65ddd49866a4e62e)

Author SHA1 Message Date
Istvan Csomortani 02ada3bbf7 a10gx: Delete input/output delay definitions
All input and output delays should be referenced to a virtual clock.

If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
2020-08-11 10:14:18 +03:00
Istvan Csomortani f1a0946a5d daq3: Delete redundant timing constraint
Delete none generic timing constarints related to the memory interface.
Set optimization mode to default.
2020-08-11 10:14:18 +03:00
Adrian Costina 22df03f9a4 daq3: A10GX, overconstrained failing paths 2017-10-28 08:21:50 +01:00
Adrian Costina fe1adb6e4f daq3: A10GX, updated to the ADI JESD204
- changed lane rate to 12.33Gbps
- added dac fifo
2017-10-25 14:45:27 +01:00
Istvan Csomortani df70a6605c daq3/a10gx: Add external falsh support 2017-10-06 08:45:33 +01:00
Rejeesh Kutty 6100a697e8 daq3/a10gx- alt 16.1 updates 2017-06-07 10:23:20 -04:00
Rejeesh Kutty 7c363cd5a7 daq3/a10gx/system_constr.sdc- fix typo 2017-02-03 09:26:07 -05:00
Istvan Csomortani fcd56a2f90 daq3/a10gx: Update project to the new GT framework
- Update common script
- Update system_top, some port names were changed
- Update constraint files
2016-10-10 16:22:08 +03:00
Adrian Costina 92c580a84d daq3: A10GX, updated project to the TCL flow 2016-07-08 12:00:37 +03:00
Rejeesh Kutty d2fc64d130 daq3/a10gx: updates 2016-05-27 08:37:47 -04:00
Rejeesh Kutty b0fef1122e daq3/a10gx: copy 2015-12-10 09:41:37 -05:00