2 Commits (8fc1f046a40c3a56bafd7798e088ea9f6a428d13)

Author	SHA1	Message	Date
Istvan Csomortani	c4152627f0	plddr3: Sync adc_wcnt_int to adc_wr and fix adc_dwr pulse width ... The adc_wcnt_int must be synchronized to adc_wr. The adc_dwr signal pulse width was to long, it needs to be just one adc_clk cycle.	2014-12-09 13:59:19 +02:00
Rejeesh Kutty	81b4cd532d	axi_fifo2s: include bus width/clock transfer	2014-11-12 14:43:38 -05:00