3859cba186
adrv9371x/zc706: Add PL_DDR FIFO to the design
2016-05-27 14:13:55 +03:00
3b6a36e3e2
axi_dacfifo: Increase the ASYM_MEM depth in the DAC side
...
Increase the asymetric memory depth on the DAC side. Increase the
data width of the grey coder and decoder.
The controller fills up the CDC memory with three AXI burst, to prevent
underflow on the wrap arounds.
2016-05-27 14:13:55 +03:00
d0b40afb45
zc706/common: Fix PL_DDR3 fifo integration script
2016-05-27 14:13:55 +03:00
c8d4f956e7
axi_dacfifo: Update the read back logic
...
Update the readback logic of the FIFO. The controller uses a
relative address counter, which counts the DMA beats. The readback
logic uses the last value of that counter to define the wrapping
address. The aditional data from the last AXI burst, if there is any,
will be dropped.
2016-05-27 14:13:55 +03:00
88e0cfec42
axi_dacfifo: The AXI read and write have the same properties
...
AXI read and AXI write channel have the same SIZE and LENGTH.
2016-05-27 14:13:55 +03:00
aca3038919
axi_dacfifo: No overflow for DAC
2016-05-27 14:13:55 +03:00
81ade7f26c
axi_dacfifo: Fix resets
...
DMA side: axi_resetn is used to reset the address counters
DAC side: GT tx_rst is used to reset the last_address register
2016-05-27 14:13:55 +03:00
578376c8fe
axi_dacfifo: Add bypass logic
2016-05-27 14:13:55 +03:00
f10c1e6e93
axi_hdmi_tx: Remove hdmi_full_range register
2016-05-27 14:04:40 +03:00
9c6e80fca2
daq3/a10gx- qsys modifications
2016-05-24 03:15:45 -04:00
05ac271aff
daq3/a10gx- qsys modifications
2016-05-24 03:15:24 -04:00
39d23032f1
daq2- qsys updates
2016-05-23 10:55:44 -04:00
d254fa841b
library- altera updates
2016-05-23 10:55:07 -04:00
0d1c4d232e
a10soc- updates-1
2016-05-20 16:14:57 -04:00
3f00614bc7
axi_jesd_xcvr: rx/tx only select
2016-05-20 16:13:36 -04:00
f1a603a3b1
ad9371- altera ip
2016-05-20 15:16:36 -04:00
09520709b0
make updates
2016-05-20 12:35:45 -04:00
f92e8509bb
adrv9371x- added
2016-05-20 11:46:25 -04:00
b5b05bb9d1
axi_ad9371: added
2016-05-20 11:41:54 -04:00
50d018fc11
arradio- rfifo/wfifo added
2016-05-18 13:24:13 -04:00
bf0b90229a
rfifo/wfifo- qsys ip
2016-05-18 13:24:13 -04:00
7fdaee186c
upack/cpack- qsys ip
2016-05-18 13:24:13 -04:00
a262eb7ab3
ad9361- output-rst - associated-rst issue?
2016-05-18 13:24:13 -04:00
e15893444c
upack- fix interface names
2016-05-18 13:24:13 -04:00
285cbc7225
xfifo- fix sdc/xdc names
2016-05-18 13:24:13 -04:00
d7f0bd1b76
ad9361- add reset sink
2016-05-18 13:24:13 -04:00
bb4ed42a93
ad9361- add missing wires
2016-05-18 13:24:13 -04:00
42b0fabd40
axi_hdmi_tx_core: Fixed data path
2016-05-17 14:41:18 +03:00
e345953bdd
arradio- updates
2016-05-16 12:19:38 -04:00
68329de738
ad9361- interface updates
2016-05-16 12:19:38 -04:00
421c0519f4
util_rfifo- updates
2016-05-16 12:19:38 -04:00
e05204a86d
util_cpack: interface updates
2016-05-16 12:19:38 -04:00
6bc05fc844
ad_*_in: register post-iob
2016-05-16 12:19:38 -04:00
cd7c9c99ed
ad_*_clk: altera-pll not supported by qsys flow
2016-05-16 12:19:38 -04:00
4fbff45e27
util_wfifo- updates
2016-05-16 12:19:38 -04:00
f515885fc4
util_wfifo: altera ip
2016-05-16 12:19:38 -04:00
58a2a3259c
util_rfifo: updates
2016-05-16 12:19:38 -04:00
82d43783f1
util_rfifo: altera ip
2016-05-16 12:19:38 -04:00
31671bf9d5
util_rfifo: constraints
2016-05-16 12:19:38 -04:00
72151bb1a6
a10gx: Updated base design to include MMU
2016-05-13 18:44:41 +03:00
f3f5353944
zcu102- updates
2016-05-10 15:40:41 -04:00
16e3a0e569
zcu102- updates
2016-05-10 15:40:41 -04:00
aadb220a3f
zcu102- updates
2016-05-10 15:40:41 -04:00
e1350018da
zcu102- updates
2016-05-10 15:40:41 -04:00
a6411dbd63
zcu102- added
2016-05-10 15:40:41 -04:00
e8fbdd0f5d
zcu102: zynq ultrascale
2016-05-10 15:40:41 -04:00
0041bf69be
c5soc- remove unused hps ports
2016-05-09 13:54:08 -04:00
89b20f2a35
c5soc- remove unused hps ports
2016-05-09 13:54:08 -04:00
3871d3ce2b
ad9361-c5/a10 - updates
2016-05-09 13:54:08 -04:00
9cd6e2da51
quartus-mess- altddio direct instantiation
2016-05-09 13:54:08 -04:00
Istvan Csomortani
AndreiGrozav
Rejeesh Kutty
Adrian Costina