Commit Graph

270 Commits (8dc2161870dd9f8657ea94a24cb825bf624a3e84)

Author SHA1 Message Date
Lars-Peter Clausen 69a23ecde3 avl_adxcvr: Simplify TX lane mapping
Currently the TX lane mapping is implemented by having to connect tx_phy_s_* to
the tx_ip_s_* and the tx_phy_d_* to the tx_ip_d_* signals in the system
qsys file in the desired order.

Re-work things so that instead the lane mapping is provided through the
TX_LANE_MAP parameter. The parameter specifies in which order logical lanes
are mapped onto the physical lanes.

The appropriate connections are than made inside the core according to this
parameter rather than having to manually connect the signals externally.

In order to generate a 1-to-1 mapping the TX_LANE_MAP parameter can be left
empty.

This change slightly reduces the boiler-plate code that is necessary to
setup the transceiver.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-03 17:57:58 +02:00
Rejeesh Kutty 207f00a752 projects/ remove upack dma_xfer_in 2017-07-31 09:12:05 -04:00
Lars-Peter Clausen f0655e63a6 avl_adxcvr: Derive PLL and core clock frequency from lane rate
The PLL frequency must be half of the lane rate and the core clock rate
must be lane rate divided by 40. There is no other option, otherwise things
wont work.

Instead of having to manually specify PLL and core clock frequency derive
them in the transceiver script. This reduces the risk of accidental
misconfiguration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 15:11:08 +02:00
Lars-Peter Clausen 2e173201d4 daq2: daq2_qsys.tcl: Use sys_dma_clk
Use the sys_dma_clk clock module for clock and reset signals of the data
path, rather than using the A10GX specific sys_ddr3_cntrl signals. This
enables compatibility for all Altera/Intel platforms.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-17 17:38:20 +02:00
Lars-Peter Clausen 0360e8587e Connect JESD204 interrupts
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
Lars-Peter Clausen 2e8be3d7a6 daq2: Provide DAC lane map
Provide the correct lane mapping for the DAQ2 DAC lanes which do not follow
a 1-to-1 mapping between physical and logical lanes due to PCB layout
constraints.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Adrian Costina b7ca17f02b scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Rejeesh Kutty d1bab7ddb9 hdlmake.pl- updates 2017-06-06 16:10:05 -04:00
Rejeesh Kutty 3f92381bd0 daq2/a10gx- project/constraint updates 2017-06-06 16:09:15 -04:00
Rejeesh Kutty dd48929327 hdlmake.pl - updates 2017-06-06 12:25:35 -04:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 4c998d1e18 make: Update make files 2017-05-25 15:12:17 +03:00
Lars-Peter Clausen 0ec92d3153 daq2: Convert to ADI JESD204
Convert the DAQ2 project to the ADI JESD204 link layer cores. The change is
very straight forward, but a matching change on the software side is
required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 01aea161fa Create CDC helper library
Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Rejeesh Kutty 36037a76f8 kcu105- vivado now depends on order of constraints? 2017-05-19 11:21:36 -04:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Rejeesh Kutty c4b4bdc415 daq2/a10gx- constraints remove 16.0 2017-05-16 10:09:42 -04:00
Rejeesh Kutty cfcb269d38 a10gx- change ddr to 1G 2017-05-15 09:32:36 -04:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Lars-Peter Clausen 7a53b99b8b daq2: zc706: Increase DAC FIFO size
Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is
quite a limiting size for practical applications. Increase the size to 1MB
to allow loading larger waveforms.

In this configuration the DAC FIFO will use half of the available BRAM
cells in the FPGA. This still leaves quite a few BRAMs available for
user application logic added to the design. If a user design should run out
of BRAMs nevertheless they can reduce the FIFO size, if not required by the
application, to free up some cells.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-28 12:29:01 +02:00
Istvan Csomortani b92703b59f daq2: Fix typo 2017-04-24 15:44:45 +03:00
Istvan Csomortani b9bc85dd1a daq2/zcu102: Update tcl command for IP configuration 2017-04-24 11:51:12 +03:00
Istvan Csomortani 871cfa7e5b daq2/kcu105: Update tcl command for IP configuration 2017-04-24 11:50:35 +03:00
Adrian Costina 942d69a30c Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Rejeesh Kutty 454e6c0382 daq2- ad-ip-instance & ad-ip-parameter 2017-04-06 13:04:53 -04:00
Rejeesh Kutty 8063ba2b66 make updates 2017-03-20 16:05:18 -04:00
Istvan Csomortani 191669ad28 daq2_common: Fix the dac_rst for DAC FIFO 2017-03-07 16:13:46 +02:00
Istvan Csomortani 4a6fe54fcf daq2_common: Update common scripts
Add new port connection for util_dacfifo
2017-03-03 18:49:10 +02:00
AndreiGrozav b78e9d8c27 daq2_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V 2017-03-01 11:32:17 +02:00
Rejeesh Kutty fb4a583613 projects/system_bd- adc/dac fifo board designs 2017-02-27 16:06:39 -05:00
Rejeesh Kutty 6b1a8852a9 dacfifo- bypass port name change 2017-02-27 16:06:39 -05:00
Rejeesh Kutty edd5e9570f file renamed; sed output; fingers crossed 2017-02-22 15:56:37 -05:00
Rejeesh Kutty 096274a033 daq2/zcu102- fix refclock pin swap 2017-02-03 09:26:07 -05:00
Rejeesh Kutty 85ff496c12 daq2/a10gx- gpio match with others 2017-02-01 20:54:56 -05:00
Rejeesh Kutty 4a783d523d projects/altera* - default & common qsys commands 2016-12-20 16:27:44 -05:00
Adrian Costina 8ebc8fe4e2 updated makefiles 2016-12-09 23:06:41 +02:00
Rejeesh Kutty daa3df4b96 projects/- xcvr updates 2016-11-22 16:23:05 -05:00
Rejeesh Kutty b1a9bd96f1 daq2: xcvr pll changes 2016-11-22 12:53:29 -05:00
AndreiGrozav cac4057449 daq2/common: Altera updates 2016-11-15 16:03:52 +02:00
Rejeesh Kutty cb97bc500a hdlmake updates 2016-10-17 16:29:57 -04:00
Rejeesh Kutty 5bb77109ca daq2/a10gx- make fix 2016-10-10 13:03:44 -04:00
Rejeesh Kutty 905e29eb01 hdlmake- altera 2016-10-10 12:55:55 -04:00
Rejeesh Kutty e5cf417576 daq2/mb- xcvr procedures 2016-10-10 12:51:30 -04:00
Rejeesh Kutty 273073a584 daq2/kcu105- xcvr procedure 2016-10-10 11:12:47 -04:00
Rejeesh Kutty ffaf78665f daq2- xcvr procedures 2016-10-06 14:44:20 -04:00
Rejeesh Kutty 3b55822db3 daq2- xcvr connect 2016-10-06 14:09:27 -04:00
Rejeesh Kutty 721ee98a06 zcu102- misc fixes 2016-10-06 10:18:14 -04:00