pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Laszlo Nagy	14307856ea	xilinx:adxcvr: PRBS support The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal PRBS generators and checkers allowing the testing the multi-gigabit serial link at the physical layer without the need of the link layer bringup.	2021-01-12 13:40:42 +02:00
Istvan Csomortani	ac2e5a9dac	constraints: Update constraints Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.	2017-02-24 13:43:32 +02:00
Rejeesh Kutty	2b7c976be5	xcvr- altera/xilinx split	2016-08-04 13:26:10 -04:00

Author

SHA1

Message

Date

Laszlo Nagy

14307856ea

xilinx:adxcvr: PRBS support

The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal
PRBS generators and checkers allowing the testing the multi-gigabit serial link
at the physical layer without the need of the link layer bringup.

2021-01-12 13:40:42 +02:00

Istvan Csomortani

ac2e5a9dac

constraints: Update constraints

Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.

2017-02-24 13:43:32 +02:00

Rejeesh Kutty

2b7c976be5

xcvr- altera/xilinx split

2016-08-04 13:26:10 -04:00

3 Commits (8d388dd4f28debd0dd08c3d0cd74a5a06009dea3)