Commit Graph

70 Commits (8d388dd4f28debd0dd08c3d0cd74a5a06009dea3)

Author SHA1 Message Date
Laszlo Nagy 6f4053f3b0 util_adxcvr: Fix PRBS synchroniser typo
The control lines for TX PRBS must be synchronized using the TX clock.
2021-01-29 14:01:25 +02:00
Laszlo Nagy 14307856ea xilinx:adxcvr: PRBS support
The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal
PRBS generators and checkers allowing the testing the multi-gigabit serial link
at the physical layer without the need of the link layer bringup.
2021-01-12 13:40:42 +02:00
Istvan Csomortani 32eeedb660 makefile: Update makefiles 2020-05-07 08:41:49 +01:00
Laszlo Nagy 8af5f65ff2 util_adxcvr: enable EyeScan for GTY4 2020-03-10 18:17:38 +02:00
Laszlo Nagy ea06fcd7b6 util_adxcvr: add GTY4 parameters for 15.5Gbps lanerate 2020-02-10 09:48:17 +02:00
Laszlo Nagy 253b1149ad library/xilinx/util_adxcvr: merge GTY and GTH prefixed parameter
parameters with same names were duplicated with transceiver specific
names due different default values.
This does not scales very well.

Use same name for the parameters as for other parameters and do the
default value handling in the IP configuration layer.
2020-02-10 09:48:17 +02:00
Adrian Costina 39d19ef401 util_adxcvr: Add additional parameters allowing for GTH4 RX 15Gbps rates 2019-11-11 14:46:09 +02:00
Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
Adrian Costina 81bcf9f6fc util_adxcvr: Cleanup whitespaces for GTY4 instantiations 2019-06-25 15:35:49 +03:00
Adrian Costina a0d738e1a9 util_adxcvr: Add GTH parameters for line rate of 15Gbps 2019-05-24 11:05:36 +03:00
Laszlo Nagy f45408d6a9 util_adxcvr: Expose GTY4 parameters required for 15Gbps link
These parameters must be overwritten when the link is at 15Gbps.
The parameters have a GTY4_ prefix since the same parameters are shared
between GTY4 and GTH4 having different default values.
2019-05-09 15:33:15 +03:00
Istvan Csomortani 42d2738a30 axi/util_adxcvr: Add GTYE4 transceiver support 2019-04-12 16:19:54 +03:00
AndreiGrozav 23841478c6 Remove library/scripts/common_bd.tcl
Remove the script from the file list of the IPs that previously used it.
axi_clkgen: Add independent adi_auto_assign_device_spec proc
2019-04-09 16:07:14 +03:00
AndreiGrozav 7dcaaea04e library: Update scripts/adi_ad_ip.tcl and IPs
Fix library makefiles dep list using generic vendor info reg

Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure.
This change will simplify the process of generating makefiles for each library.
Removing the bd.tcl script from the adi_ip_files list will remove it from the
make dependency list.
2019-04-09 16:07:14 +03:00
AndreiGrozav 4ae5a6d3d8 library/IPs: Auto-generate bd.tcl Update
Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to
auto-generate bd.tcl for:

  - axi_ad5766/axi_ad5766_ip.tcl
  - axi_ad6676/axi_ad6676_ip.tcl
  - axi_ad9122/axi_ad9122_ip.tcl
  - axi_ad9144/axi_ad9144_ip.tcl
  - axi_ad9152/axi_ad9152_ip.tcl
  - axi_ad9162/axi_ad9162_ip.tcl
  - axi_ad9250/axi_ad9250_ip.tcl
  - axi_ad9265/axi_ad9265_ip.tcl
  - axi_ad9361/axi_ad9361_ip.tcl
  - axi_ad9371/axi_ad9371_ip.tcl
  - axi_ad9434/axi_ad9434_ip.tcl
  - axi_ad9467/axi_ad9467_ip.tcl
  - axi_ad9625/axi_ad9625_ip.tcl
  - axi_ad9671/axi_ad9671_ip.tcl
  - axi_ad9680/axi_ad9680_ip.tcl
  - axi_ad9684/axi_ad9684_ip.tcl
  - axi_ad9739a/axi_ad9739a_ip.tcl
  - axi_ad9963/axi_ad9963_ip.tcl
  - axi_adrv9009/axi_adrv9009_ip.tcl
  - axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl
  - axi_hdmi_tx/axi_hdmi_tx_ip.tcl
  - xilinx/axi_adxcvr/Makefile
  - xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
  - xilinx/util_adxcvr/Makefile
  - xilinx/util_adxcvr/util_adxcvr_ip.tcl
2019-03-30 11:26:11 +02:00
AndreiGrozav 66823682b6 Add FPGA info parameters flow
Common basic steps:
- Include/create infrastructure:

   * Intel:
       - require quartus::device package
       - set_module_property VALIDATION_CALLBACK info_param_validate

   * Xilinx
       - add bd.tcl, containing init{} procedure. The init procedure will be
         called when the IP will be instantiated into the block design.
       - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
       - create GUI files

- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files

axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
2019-03-30 11:26:11 +02:00
Adrian Costina 47f7894881 util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4) 2019-02-11 17:20:08 +02:00
Adrian Costina e1f15f946b axi/util_adxcvr: Add register to control eyescan reset 2018-11-16 14:18:33 +02:00
Adrian Costina 98d3d44fd1 axi_adxcvr: Fix eyescan support for ultrascale plus devices 2018-11-16 14:18:33 +02:00
Istvan Csomortani 42127c07fc util_adxcvr: Expose QPLL and CPLL *_CFG attributes 2018-10-04 14:37:02 +03:00
Istvan Csomortani 740715c6b3 util_adxcvr: Update GHTE4 input port from the wizard 2018-10-04 14:37:02 +03:00
Istvan Csomortani 0d3e05b311 axi|util_adxcvr: Expose TX configurable driver ports
Expose the TX configurable driver ports, more specifically the
TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This
provides a soft tunning capability of the transmit side of the
transceivers, in cases where the insertion loss of the channel is too
high or low, comparing to the default value supported by the default
configuration of the GTs.

You can find information about these configuration ports under the
section called 'TX Configurable Driver' in the GT transceivers user
guide. (UG476, UG576)
2018-10-04 14:37:02 +03:00
Istvan Csomortani 8fc6ee8851 util_adxcvr: Define all GTHE4 attribute in binary
This commit does not contain any functional modification.

Because the wizard generates the attributes in binary, we should use
binary mode too, so we can compare different configurations more easily.
2018-10-04 14:37:02 +03:00
Istvan Csomortani e31cfe5639 util_adxcvr_xch: GTHE4 connect CPLL_FBDIV_45 attribute 2018-10-04 14:37:02 +03:00
Istvan Csomortani 99a1768813 Revert "util_adxcvr: Update GTH4 parameter values to work with DAQ3 at 12.33Gbps lane rate"
This reverts commit 9a74a40c49.
2018-10-04 14:37:02 +03:00
Istvan Csomortani af5c71a9b2 axi|util_adxcvr: Delete reset interface inference for PLL resets
The Xilinx's reset interface expect that every reset have an associated
interface and clock signal. The tool will try to find its clock and interface,
and automatically associated clock signal to it.

The PLL resets are individual asynchronous resets. To simplify the design
and avoid invalid critical warnings all the reset interface inference
for the PLL resets were removed.
2018-08-23 18:41:48 +03:00
Adrian Costina 9a74a40c49 util_adxcvr: Update GTH4 parameter values to work with DAQ3 at 12.33Gbps lane rate
Left new parameters values in binary, as that's the way they are generated with the wizard, so future diff should be easier
2018-08-23 18:06:32 +03:00
Lars-Peter Clausen f647dd4c0a xilinx: util_adxcvr: Add support for lane polarity inversion
Some designs choose to swap the positive and negative side of the of the
JESD204 lanes. One reason for this would be because it can simplify the
PCB layout. The polarity is in most cases also only applied to a subset of
the used lanes.

Add support for this to the util_adxcvr module. This done by adding new
parameter to the modules that allows to specify a per lane polarity
inversion. Each bit in the parameter corresponds to one lane. If the bit is
set the polarity is inverted for his lane. E.g. setting the parameter to
0xc will invert the 3rd and 4th lane.

The setting is forwarded to the Xilinx transceiver for the corresponding
lane.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-02 09:37:23 +02:00
Lars-Peter Clausen 2b914d33c1 Move Altera IP core dependency tracking to library Makefiles
Currently the individual IP core dependencies are tracked inside the
library Makefile for Xilinx IPs and the project Makefiles only reference
the IP cores.

For Altera on the other hand the individual dependencies are tracked inside
the project Makefile. This leads to a lot of duplicated lists and also
means that the project Makefiles need to be regenerated when one of the IP
cores changes their files.

Change the Altera projects to a similar scheme than the Xilinx projects.
The projects themselves only reference the library as a whole as their
dependency while the library Makefile references the individual source
dependencies.

Since on Altera there is no target that has to be generated create a dummy
target called ".timestamp_altera" who's only purpose is to have a timestamp
that is greater or equal to the timestamp of all of the IP core files. This
means the project Makefile can have a dependency on this file and make sure
that the project will be rebuild if any of the files in the library
changes.

This patch contains quite a bit of churn, but hopefully it reduces the
amount of churn in the future when modifying Altera IP cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 35a39ba2e6 Regenerate library Makefiles using the new shared Makefile include
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.

It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Istvan Csomortani 571b721274 util_adxcvr: CPLLPD should be used for reset
For CPLL reset the CPLLPD ports should be used, instead of the
CPLLRESET. The recommended reset width is above 2us.
See UG576 pg. 60 for more detail.
2018-04-11 15:09:54 +03:00
Adrian Costina a5407702bb util_adxcvr: Don't show reset ports for disabled lanes 2018-04-11 15:09:54 +03:00
Adrian Costina 74b922f9f8 axi_*: Infer clock and reset signals of an IP
A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.

The following IPs tcl script was updated:
  - axi_ad9434
  - axi_hdmi_tx
  - util_cpack
  - util_adxcvr
  - axi_ad6676
  - axi_ad9625
  - axi_ad9379
  - axi_ad9265
  - util_tdd_sync
  - util_rfifo
  - util_wfifo
  - axi_ad9361
  - axi_ad9467
  - util_upack
  - axi_dacfifo
  - axi_ad9152
  - axi_ad9680
  - util_clkdiv
  - axi_ad9122
  - axi_ad9684
  - axi_mc_speed
  - axi_mc_current_monitor
  - axi_mc_controller
  - util_gmii_to_rgmii
  - util_adxcvr
  - axi_ad9379
  - axi_hdmi
  - library
  - axi_fmcadc5_sync
  - util_adcfifo
  - util_mfifo
  - axi_jesd204_rx
  - axi_jesd204_tx
  - axi_ad9361
  - axi_adxcvr_ip
2018-04-11 15:09:54 +03:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
Rejeesh Kutty 8aba66477e util_adxcvr- defaults for es 2017-08-08 11:03:38 -04:00
Lars-Peter Clausen 121e04e94e util_adxcvr: Bring back channel 8
This was accidentally deleted in commit 6d4430cfda
("axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access").

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-29 13:16:48 +02:00
Lars-Peter Clausen 6d4430cfda axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access
When using non-broadcast access to the GT DRP registers lane filtering is
done on both sides. The ready and data signals are filtered in the in the
axi_adxcvr module and the enable signal is filtered in the util_adxcvr
module. This works fine as long as both sides use the same transceiver IDs.
E.g. channel 0 of the axi_adxcvr module is connected to channel 0 of the
util_adxcvr module.

But this is not always the case. E.g. on the ADRV9371 platform there are
two RX axi_adxcvr modules (RX and RX_OS) connected to the same util_adxcvr.
The first axi_adxcvr uses lane 0 and 1 of the util_adxcvr, the second uses
lane 2 and 3.

Non-broadcast access for the first RX axi_adxcvr module works fine, but
always generates a timeout for the second axi_adxcvr module. This is
because lane 0/1 of the axi_adxcvr module is connected to lane 2/3 of the
util_adxcvr and when ID based filtering is done both can't match at the
same time.

To avoid this perform the filtering for all the signals in the axi_adxcvr
module. This makes sure that the same base ID is used.

This also removes the sel signal from the transceiver interfaces since it
is no longer used on the util_adxcvr side.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-28 17:30:51 +02:00
Rejeesh Kutty dd48929327 hdlmake.pl - updates 2017-06-06 12:25:35 -04:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Lars-Peter Clausen d883aabcc1 adi_ip.tcl: Use analog.com for interface vendor
Currently the scripts use 'analog.com' as the vendor property for IP cores,
but 'ADI' for interfaces.

Make things consistent by using 'analog.com' for both interfaces as well
as IP cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-24 18:10:15 +02:00
Rejeesh Kutty 393577c911 util_adxcvr- 2016.4 gthe4 updates 2017-05-18 14:49:18 -04:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani ac2e5a9dac constraints: Update constraints
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
Adrian Costina 573959c826 Makefiles: fixed axi_adxcvr/util_adxcvr Makefiles to include interfaces dependancy 2017-02-23 16:16:34 +02:00
Istvan Csomortani 5fa6dba333 Make: Update Makefiles 2017-02-10 16:32:58 +02:00
Adrian Costina 8ebc8fe4e2 updated makefiles 2016-12-09 23:06:41 +02:00
Rejeesh Kutty 8f562fd069 xcvr updates- board procedure 2016-11-22 14:43:36 -05:00