Istvan Csomortani
|
f326c03ff3
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axi_dacfifo: Define constraint for bypass
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
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2017-02-24 12:35:42 +02:00 |
|
Istvan Csomortani
|
b9d3039568
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axi_dacfifo: Register the dac_valid signals
|
2017-02-24 12:34:58 +02:00 |
|
Istvan Csomortani
|
debc6e2066
|
axi_dacfifo: Data from DMA is validated with dma_ready too
|
2017-02-24 12:32:25 +02:00 |
|
Istvan Csomortani
|
dfcd5214a0
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axi_dacfifo: axi_dvalid should come from dacfifo_rd module
|
2017-02-24 12:28:46 +02:00 |
|
Istvan Csomortani
|
1fce57f6c3
|
axi_dacfifo: Redesign the bypass functionality
|
2017-02-23 17:32:31 +02:00 |
|
Istvan Csomortani
|
e3ac341aad
|
axi_dacfifo: Fix constraints
|
2017-02-21 14:45:18 +02:00 |
|
Istvan Csomortani
|
981a61bf16
|
axi_dacfifo: Clean up the axi_dacfifo_wr.v module
|
2017-02-17 18:40:02 +02:00 |
|
Istvan Csomortani
|
f10866e4c3
|
axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter
|
2017-02-16 19:54:41 +02:00 |
|
Istvan Csomortani
|
95a4ea20c8
|
axi_dacfifo: Delete redundant parameter BYPASS_EN
|
2017-02-16 19:53:44 +02:00 |
Adrian Costina
|
8ebc8fe4e2
|
updated makefiles
|
2016-12-09 23:06:41 +02:00 |
Rejeesh Kutty
|
9defccef70
|
dacfifo- axi address map fixes
|
2016-09-27 14:48:23 -04:00 |
|
Istvan Csomortani
|
3b0c1e02fc
|
axi_dacfifo: Move IP to library/xilinx
|
2016-09-15 11:38:16 +03:00 |