6 Commits (8ccd8d87bb1fc7976dbaed223fb5e8e416013a8f)

Author	SHA1	Message	Date
Adrian Costina	89f7aadfb1	fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output ... This will allow for the transceivers to be reset by the axi_jesd_xcvr core	2016-02-23 11:31:07 +02:00
Adrian Costina	0f37dd6424	fmcjesdadc1: Fixed project ... - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release	2016-02-19 14:09:57 +02:00
Adrian Costina	9281eb2c33	fmcjesdadc1: Updated common altera design	2015-11-24 15:38:58 +02:00
Adrian Costina	36f71ea59b	fmcjesdadc1: common altera, fixed dmac configuration and connection. Connected reset for cpack	2015-07-28 12:33:24 +03:00
Rejeesh Kutty	d8e2196c75	fmcjesdadc1- board qsys	2015-07-22 15:44:04 -04:00
Rejeesh Kutty	d66387f482	fmcjesdadc1- board qsys	2015-07-22 15:23:39 -04:00