ab1f9bed10
wfifo: remove srl from sync registers
2015-06-05 12:44:04 -04:00
da8915296b
pack: ip scripts
2015-06-05 09:20:08 -04:00
6338dfd8b7
ad9361: ip defaults & rst output
2015-06-05 09:19:39 -04:00
cb0324c2b1
wfifo: multi-channel option
2015-06-05 09:19:05 -04:00
2e877389b2
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 18:09:49 +03:00
3b1ea7e528
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
...
598ece4c8d
2015-06-04 18:09:47 +03:00
6548bcd71f
axi_ip- constraints: add rst path
2015-06-04 10:53:13 -04:00
e02273781f
ad_rst- non lpm version
2015-06-04 10:53:12 -04:00
91b0f70972
library: remove drp cntrl
2015-06-02 09:58:57 -04:00
2b5abf74d7
util_upack: Show upack_valid only if the channel is activated
2015-06-02 11:36:06 +03:00
297e885981
library- drp moved to up-clock domain
2015-06-01 14:52:52 -04:00
e7470036bf
library- drp moved to up clock
2015-06-01 13:39:26 -04:00
c6ebab7393
library- drp moved to up clock
2015-06-01 13:39:26 -04:00
aa24c442f5
a10gx- no-ddr
2015-06-01 11:00:01 -04:00
d7b68c39ef
altera- sdc
2015-06-01 10:59:59 -04:00
2a0bdbebf2
altera- sdc
2015-06-01 10:59:58 -04:00
92fc0e050d
altera- common sdc
2015-06-01 10:59:57 -04:00
83df53d9bf
adc_common: Updated version because the delay registers have been changed
2015-05-25 17:18:14 +03:00
1ef83bd88b
axi_ad9671: Updated port names. Fixed synchronization of the rx_sof with the ad_jesd_align module, so that data valid is assigned correctly
2015-05-23 00:16:27 +03:00
660c84e01c
axi_ad9434 : Update the IO delay interface
2015-05-22 19:47:09 +03:00
0c6ef203c0
iobuf: do is a system-verilog keyword
2015-05-21 14:06:13 -04:00
dc2eeebf2f
upack: gen-name
2015-05-21 14:06:12 -04:00
5c6340e927
dmac: clock-typo
2015-05-21 14:06:11 -04:00
e05ff26406
ad9144: ddata-typo
2015-05-21 14:06:09 -04:00
8d78217f7b
ad9680: missing prot. ports
2015-05-21 14:06:08 -04:00
4c6a3afc88
ad9144: missing prot. ports
2015-05-21 14:06:06 -04:00
a059290cf5
Remove axi_ad7175
...
This core has been superseded by the SPI Engine framework in combination
with the axi_generic_adc core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
c53f8c15ee
Add CN0363 project
...
Add support for the CN0363 (colorimeter) board connected to the ZED board.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
d43ba44d0f
Add util_sigma_delta_spi peripheral
...
The util_sigma_delta_spi peripheral can be used to seperate the interleaved
SPI bus and DRDY signals for a ADC from the Analog Devices SigmaDelta
family.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
e6b58e8a20
Add SPI Engine framework
...
SPI Engine is a highly flexible and powerful SPI controller framework. It
consist out of multiple sub-modules which communicate over well defined
interfaces. This allows a high degree of flexibility and re-usability while
at the same time staying highly customizable and easily extensible.
Currently included are four components:
* SPI Engine execution module: The excution module is responsible for
handling the low-level physical interface SPI logic.
* SPI Engine AXI interface module: The AXI interface module allows
memory mapped acccess to a SPI bus control stream and can be used to
implement a software driver that controls the SPI bus.
* SPI Engine offload module: The offload module allows to store a
predefined SPI Engine command and data stream which will be send out
when a external trigger signal is asserted.
* SPI Engine interconnect module: The interconnect module allows to
combine multiple control streams into a single stream giving multiple
control modules access to a execution module.
For more information see: http://wiki.analog.com/resources/fpga/peripherals/spi_engine
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
a5b452cc27
Add axi_generic_adc core
...
The axi_generic_adc core is a simple core that doesn't do much more then
implementing the AXI ADC register map and routing the enable and overflow
signals to the farbic.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
033713ccb5
Add cordic demodulator module
...
The cordic_demod module takes in phase and data on s_axis interface then
performs a cordic demodulation and outputs the resulting I and Q component
data on the m_axis interface.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
cefbe3a0ff
scripts/adi_ip.tcl: Add option to specify reset interface direction
...
Allow to specify the direction of the reset signal for a interface, this is
useful if the core itself generates the reset signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
6b9906b22b
Refresh Makefiles
...
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
5ac7ebb8a3
axi_mc_*: Removed delay pins from up_adc_common
2015-05-21 14:03:58 +03:00
465f7dff88
library/util_jesd_align -added
2015-05-20 15:38:43 -04:00
9762c65868
library- jesd-align port name change
2015-05-20 14:25:21 -04:00
da0409b5a6
library- qsys components
2015-05-20 11:51:50 -04:00
9b425736ac
library: altera ip modifications
2015-05-20 10:41:21 -04:00
d48d3f4aa3
scripts/ip-alt- added
2015-05-20 09:11:18 -04:00
e918588a4b
library: remove axi-min-size parameter
2015-05-19 13:07:48 -04:00
4fb1be0672
ad9680: delay changes
2015-05-19 12:53:56 -04:00
af7afd7366
ad9671: delay changes
2015-05-19 12:53:56 -04:00
09a05fe9d8
ad9652: delay changes
2015-05-19 12:53:56 -04:00
13156593f8
ad9643: delay changes
2015-05-19 12:53:56 -04:00
c8d3c04a05
ad9625: delay changes
2015-05-19 12:53:56 -04:00
f53204f9f9
ad9467: delay changes
2015-05-19 12:53:56 -04:00
fe0ceb2530
delay-cntrl updates
2015-05-18 15:23:10 -04:00
304a202d67
delay-cntrl updates
2015-05-18 14:57:05 -04:00
2e257db109
delay-cntrl updates
2015-05-18 14:53:24 -04:00
0877c252ad
delay-cntrl changes
2015-05-18 14:28:20 -04:00
2bad47cf4f
delay-cntrl: up-clk, direct access + tx
2015-05-18 14:28:20 -04:00
6e047f78c6
delay-cntrl: up-clk, direct access + tx
2015-05-18 14:28:20 -04:00
2c1719095d
util_axis_resize: Changed _ip.tcl format to the standard format
2015-05-18 17:25:07 +03:00
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
...
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
a07d11c3e9
axi_ad9361_tdd: Define control bits for continuous receive/transmit
2015-05-14 17:21:32 +03:00
c9c05e21c2
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 16:34:06 +03:00
7c9bc40c75
axi_ad9361&TDD: Update TDD
...
+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
2015-05-13 14:03:01 +03:00
a1d680ee6b
ad9680- add hw tcl
2015-05-12 15:06:42 -04:00
833a3de6b5
ad9680- add hw tcl
2015-05-12 15:06:39 -04:00
48c769d431
ad9144- add hw tcl
2015-05-12 14:40:38 -04:00
553f89f59d
ad9144- add hw tcl
2015-05-12 14:39:57 -04:00
4553de3ffa
ad9361- align hold
2015-05-11 11:55:01 -04:00
9934cce5d2
util_dacfifo: Add CDC logic for dma_lastaddr register.
2015-05-11 12:20:46 +03:00
2e7135c3c2
axi_ad9361_tdd: Initial commit.
...
Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 12:20:44 +03:00
14e23b106c
axi_ad9361: changed device interface module for Altera to have the same inputs as the one for Xilinx
2015-05-08 17:43:10 +03:00
12ed393d39
ad9361- framing modifications
2015-05-07 15:13:18 -04:00
a68539edf1
ad9361- framing modifications
2015-05-07 15:13:17 -04:00
176a4a4b76
ad9361: add ddr-edgesel
2015-05-06 16:58:50 -04:00
a8534a9c02
ad9361: add ddr-edgesel
2015-05-06 16:58:49 -04:00
32f7e98afd
ad9361: add ddr-edgesel
2015-05-06 16:58:47 -04:00
670850183b
axi_hdmi_tx: Updated constraints as in fmcomms2/zc702 project they were not correctly applied
2015-05-06 18:53:19 +03:00
a7c96fdac8
util_dacfifo: General clean up of the IO, input/output data has the same width
2015-05-06 16:32:44 +03:00
0613dca0b7
axi_dmac: Move the 'axis_xlast' logic into the dest_axi_stream module
2015-05-06 16:10:28 +03:00
949abcdc8f
Makefile: Updated makefiles so that the project recipe does not depend on lib
2015-05-06 14:58:29 +03:00
65af205d6b
axi_dmac: Add axis_last control signal to the Master AXI Streaming interface
...
This control signal can be overwritten by the up_axis_xlast/up_axis_xlast_en bits, in order to create a single stream, which is contains multiple streams.
This can be use to fill up the DACFIFO module.
2015-05-06 13:54:31 +03:00
233cc111d2
util_pmod_adc: Used generated clock for the ADC SPI. Works by default at 6.25MHz
2015-05-05 23:33:13 +03:00
3517b6941c
adv7511:kcu105, axi_hdmi_tx, axi_spdif_tx constraints modified so they apply to ultrascale
2015-05-05 10:06:26 +03:00
707b285669
prcfg: bb def
2015-05-04 10:24:13 -04:00
be32715ab3
axi_adcfifo: Updated constraints
2015-04-30 14:23:24 +03:00
d623f77453
axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst.
...
Resets for both up clock domain and rx clock domain are needed in some projects
2015-04-30 12:07:36 +03:00
463c4d4d28
util_wfifo: Added constraint for the resetn path
2015-04-30 12:05:02 +03:00
392ba31a07
axi_hdmi_rx: Updated constraints
2015-04-30 12:04:15 +03:00
288b9cccff
Makefile: Added makefiles for imageon_loopback project. Updated axi_ad9152, util_gmii_to_rgmii, util_wfifo to include constraints file
2015-04-28 15:22:37 +03:00
a7a2d194e9
axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core
2015-04-28 15:04:18 +03:00
c36186f75a
axi_ad9643: Added adc_rst output
2015-04-28 14:52:24 +03:00
8ee3f64a65
axi_ad9265: Added adc_rst output
2015-04-28 14:51:14 +03:00
67c581cef8
util_wfifo: Updated to be used with adc_rst from the adc_clk clock domain
2015-04-28 14:50:00 +03:00
1ad87aa27c
util_wfifo: Added constraints
2015-04-27 11:19:56 +03:00
81d4e1d9b1
axi_clkgen: Updated constraints
2015-04-27 11:19:15 +03:00
d950f5ffcd
axi_ad9122: Updated constraints
2015-04-27 11:18:52 +03:00
9fba4cb2ef
util_dacfifo: Add support for Slave AXI stream interface.
...
The FIFO can be initialized through an AXI stream interface too.
2015-04-27 10:40:55 +03:00
3a02998e9a
axi_ad9152/axi_ad9152_ip.tcl: Fix typo
...
axi_ad9152_constr.v -> axi_ad9152_constr.xdc
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-24 09:41:43 +02:00
a9924e6401
util_gmii_to_rgmii: Added constraints
2015-04-23 16:53:57 +03:00
bd06bae8c2
library: Modified the adi_ip.tcl script
...
The constraints processing order changed to "late" instead of "early", in order for all the clocks in the system to be already created when the IP constraints are applied
2015-04-23 14:31:23 +03:00
a61a195e3f
Makefiles: Updated makefiles to add the new constraints as dependecies
2015-04-23 11:16:39 +03:00
d42c0bc431
axi_jesd_gt : Added CDC and reset constraints
2015-04-23 11:03:51 +03:00
1b4e6bdc80
axi_mc_speed : Added CDC and reset constraints
2015-04-23 10:50:49 +03:00
6d28d217f1
axi_mc_current_monitor: Added CDC and reset constraints
2015-04-23 10:49:43 +03:00
d0b2d531bc
axi_mc_constroller: Added CDC and reset constraints
2015-04-23 10:47:35 +03:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
Lars-Peter Clausen