Commit Graph

14 Commits (8b6d69747b746bb2028a8259dc0bb428868bb883)

Author SHA1 Message Date
Istvan Csomortani 85a7cebc0e axi_dacfifo: Major update and redesign
Redesign the axi_dacfifo, to increase the supported datarates.
Major modifications:
  + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac
was deprecated.
  + Both the AXI write and AXI read transaction are controlled by two
FSM, to increase redability of the code.
  + Support all the possible burst lengths [0..225], handles the last
fractional burst on both sides correctly.
  + Common reset architecture throughout the design, all the internal
registers and memories are reset on the posedge of dma_xfer_req
  + Delete all Altera related sources, for Altera projects
avl_dacfifo should be used.

WIP: foobar

[WIP]axi_dacfifo: Update

axi_dacfifo: Few minor updates, almost working state
2017-08-22 09:16:21 +01:00
Istvan Csomortani 4832bc1a0c axi_dacfifo: Fix port width at axi_dacfifo_wr 2017-07-14 16:47:34 +03:00
Istvan Csomortani 75a18da971 axi_dacfifo: Increase the width of axi_last_beats and wvalid_counter
Increase the width of wvalid_counter, should be equal with awlen width.
The wvalid_counter needs to count from zero to the required burst
length. The maximum burst length is 255, so the width of the counter
have to be 8 bits. axi_last_beats will get the last axi burst length.
2017-07-06 10:24:36 +01:00
Istvan Csomortani baec8a0777 axi_dacfifo: Define DMA/DAC_MEM_ADDRESS as parameter
Make the depth of the internal CDC memories parameterizable.
2017-07-06 10:11:50 +01:00
Istvan Csomortani a0b33898d2 axi_dacfifo: Add gray coder/decoder module
Use gray coder/decoder modules, instead of functions.
This way it can be used paramterized data width on the
coders/decoders.
2017-07-06 10:01:27 +01:00
Istvan Csomortani cfa22f36bc axi_dacfifo: Fix the dma_ready signal generation
Fix the dma_ready mux in top module, and the dma_ready_out reset
logic in axi_dacfifo_wr module. Also, both write and read addresses
of the async CDC fifo (inside the axi_dacfifo_wr) should be reset
before a dma transaction starts.
2017-07-06 10:01:17 +01:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Istvan Csomortani debc6e2066 axi_dacfifo: Data from DMA is validated with dma_ready too 2017-02-24 12:32:25 +02:00
Istvan Csomortani 1fce57f6c3 axi_dacfifo: Redesign the bypass functionality 2017-02-23 17:32:31 +02:00
Istvan Csomortani 981a61bf16 axi_dacfifo: Clean up the axi_dacfifo_wr.v module 2017-02-17 18:40:02 +02:00
Istvan Csomortani 3b0c1e02fc axi_dacfifo: Move IP to library/xilinx 2016-09-15 11:38:16 +03:00