Istvan Csomortani
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1c23cf4621
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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Istvan Csomortani
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7876c8ffa4
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axi_ad9684: Add loaden and phase ports for altera support
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2016-12-06 15:24:20 +02:00 |
AndreiGrozav
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91995c082d
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axi_ad9684: Fixed up_drp_*data width
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2016-10-12 13:20:26 +03:00 |
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Istvan Csomortani
|
ad16aec101
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axi_ad9684: Fix SERDES modules
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2016-09-26 11:14:35 +03:00 |
Rejeesh Kutty
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46eddd04be
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library: port updates on mmcm
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2016-03-22 12:50:59 -04:00 |
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Istvan Csomortani
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c6cfd1a2b6
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axi_ad9684: Initial check in
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2016-01-19 11:13:45 +02:00 |