Commit Graph

1531 Commits (8aa8d3a0e5b1aea784bb3533e7e937eb788578d7)

Author SHA1 Message Date
Istvan Csomortani 4e15a21b79 spi_engine_interconnect: Delete dependency defined for S1_CTRL interface
The S1_CTRL interface is not dependent of the number of SDI lines.
2017-04-27 11:28:25 +03:00
Istvan Csomortani 4ceed4d373 util_pulse_gen: Add Makefile 2017-04-27 11:28:25 +03:00
Istvan Csomortani 18a671cdb7 spi_engine: Expose DATA_WIDTH to software
The value of DATA_WIDTH can be read back from register 0x44
The DATA_WIDTH will define the size of a word in a transaction.
2017-04-27 11:28:24 +03:00
Istvan Csomortani 801fb2281e util_pulse_gen: The valid period is stored in pulse_period_d 2017-04-27 11:28:24 +03:00
Istvan Csomortani fbccb377cc adaq7980: Add an trigger generator for SPI offload 2017-04-27 11:28:23 +03:00
Istvan Csomortani a4c422ac4c spi_engine_execution: Define port dependencies for SDI ports 2017-04-27 11:28:21 +03:00
Istvan Csomortani 045cb96744 axi_spi_engine: Define ports dependencies for up_* interface
The up_* interface ports are active just if the MM_IF_TYPE is UP_FIFO.
2017-04-27 11:27:35 +03:00
Istvan Csomortani 9cd218eb90 up_dac_common: Increase datawidth of dac_datarate
In case of high precision devices with just a simple SPI interface
for control and data, the effective data rate can be significatly
lower than the SPI clock, and more importantly there isn't any relation
between the two clock domain.
The rate is defined by a SOT (start of transfer) generator, which
initiates a SPI transfer. Taking the fact that the generator runs
on system clock (100 MHz), and the device can require smaller rate (in kHz domain),
the 7 bit dac_datarate register is just too small.

Therefor increasing to 16 bit.
2017-04-27 11:24:08 +03:00
Istvan Csomortani a2c20551a2 axi_ad5766: Add Makefiles for the core 2017-04-27 11:22:31 +03:00
Istvan Csomortani eba22892b8 axi_ad5766: Preserve consistent coding style 2017-04-27 11:21:15 +03:00
Istvan Csomortani d061104a3c util_pulse_gen: Add configuration interface for 'pulse period'. 2017-04-27 11:21:12 +03:00
Istvan Csomortani 825d46259b interface: Update spi_engine_offload_ctrl definition
Because of the new AD5766 offload module, SDO lines are
defined as 'optional'.
2017-04-27 11:19:22 +03:00
Istvan Csomortani 5c5baf3abf spi_engine: Fix CMD_FIFO_VALID generation
Because of the memory map interface mux, up_waddr_s should be used,
when cmd_fifo_in_valid is generated.
2017-04-27 11:19:20 +03:00
Istvan Csomortani 29f0ce36bb axi_ad5766: Initial commit
This core can be used in conjunction with the SPI_ENGINE, will work
as an offload module, forwarding a data stream to the SPI excecution,
received from a DMA.
2017-04-27 11:16:23 +03:00
Istvan Csomortani fb6e0d3efb spi_engine: Add dependency for unused interfaces 2017-04-27 11:16:19 +03:00
Rejeesh Kutty 5d6b018b2b ad9162- add iq swap 2017-04-26 20:54:47 -04:00
Istvan Csomortani 85a647eda8 axi_ad9361: Fix ad_cmos_out instantiations
This is a patch for 3627b89
2017-04-26 10:39:54 +03:00
Adrian Costina 7cff12107e hdlmake: Fix util_clkdiv Makefile issue. sort library master Makefile 2017-04-26 09:58:17 +03:00
Rejeesh Kutty cfd4e006b3 hdlmake updates 2017-04-25 15:46:26 -04:00
Rejeesh Kutty 804df251a6 axi_fmcadc5_sync- updates 2017-04-25 11:35:37 -04:00
Rejeesh Kutty 81570ada75 axi_fmcadc5_sync- updates 2017-04-25 11:35:37 -04:00
Rejeesh Kutty c248d5ac6a fmcadc5-sync- try sync in hdl 2017-04-25 11:35:37 -04:00
Istvan Csomortani 468965a792 altera/ad_cmos_in: Define supported DEVICE_TYPE options 2017-04-25 12:07:33 +03:00
Istvan Csomortani 52305f74c8 altera/ad_cmos_in|out: Delete redundant parameter 2017-04-25 12:06:33 +03:00
Istvan Csomortani 77eafbcccd avl_dacfifo: Update constarint file 2017-04-25 12:03:46 +03:00
Istvan Csomortani 1ef3fd4668 avl_dacfifo: Fix read/write address switching 2017-04-25 12:03:22 +03:00
Istvan Csomortani 3627b892c3 xilinx/ad_cmos_in|out: Delete redundant parameter
The LVCMOS standard is a single ended IO standard. The SINGLE_ENDED
parameter is redundant in this case.
2017-04-25 11:02:35 +03:00
Istvan Csomortani 4f4ca84813 axi_dacfifo: Fix Makefile 2017-04-24 11:46:29 +03:00
Istvan Csomortani 4007df2094 avl_dacfifo: Update constraints 2017-04-21 17:25:46 +03:00
Istvan Csomortani 89b3f45fff avl_dacfifo: Use the ad_mem_asym for altera 2017-04-21 17:25:46 +03:00
Istvan Csomortani b7bfa2d91f avl_dacfifo: Delete redundant file 2017-04-21 17:25:46 +03:00
Istvan Csomortani 180a80493b avl_dacfifo: Initial commit 2017-04-21 13:26:37 +03:00
Istvan Csomortani 5fe7a1b100 axi_dacfifo: Move the axi_dac_fifo_bypass module to util_dac_fifo_bypass 2017-04-21 13:23:03 +03:00
Istvan Csomortani 50e6fac5dd axi_hdmi_tx: Fix assignment type
The general rule of thumb is to use nonblocking assignments for
sequential always blocks.
2017-04-21 09:35:34 +03:00
Lars-Peter Clausen f319d1b5d4 axi_clkgen: Propagate clock settings to output pins
Calculate the output clock frequencies based on the input clock frequencies
and the default divider settings and configure the output clock pins
accordingly. This allows connected peripherals to infer the frequency of
the clock.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 20:36:33 +02:00
Lars-Peter Clausen af913863d4 axi_clkgen: Infer CLKIN period
Instead of having to manually specify the input clock period infer the
values from the block design. This means that less configuration parameters
need to be changed if the clock input frequency changes.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 20:36:15 +02:00
Lars-Peter Clausen fdedc9568c axi_clkgen: Add interface definitions for clock inputs/outputs
Add interface definition for the input and output clocks. This will allow
the tools to recognize them as clocks and enable things like clock
frequency propagation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 19:55:57 +02:00
Lars-Peter Clausen 15ce8cc356 axi_clkgen: Add enable parameters for secondary clock inputs/outputs
The secondary clock inputs and outputs of the axi_clkgen are rarely used.
Add enable parameters that need to be explicitly set before they are
available. This allows to hide the secondary clock pins when they are not
used in the block design.

There are currently no projects which use the secondary clock inputs or
outputs so there is no need to set these new parameters anywhere.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 19:55:57 +02:00
Lars-Peter Clausen 886c818b72 axi_clkgen: Add type hints for parameters
Vivado infers the type of floating point type parameters as integer if the
value can be expressed as an integer (i.e. decimal places are 0). To
correctly infer them as floating point parameters add types to the
parameter declaration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 19:55:56 +02:00
Lars-Peter Clausen 844521c7b1 axi_clkgen: Remove unused parameters for third clock output
The axi_clkgen has no no third clock output, no need to have parameters to
configure it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 19:55:33 +02:00
Istvan Csomortani ba6802409b axi_ad9434: ad_serdes_clk instantiation should reflect all important configurations 2017-04-20 18:52:06 +03:00
Istvan Csomortani 5b164ad4fa ad_serdes_in: Fix generate block 2017-04-20 18:50:00 +03:00
Istvan Csomortani faa5e3d667 ad_serdes_clk: Fix generate block 2017-04-20 18:49:00 +03:00
Istvan Csomortani f0da125a4e ad_mmcm_drp: Fix generate block
Can not be multiple 'if' statements inside a generate block. If there are
multiple cases use if/esle statement, but always should be one single
if/else inside a generate.
2017-04-20 18:43:37 +03:00
Istvan Csomortani 52f0eeff23 axi_ad9434: Port redeclaration as a wire is not allowed 2017-04-20 14:33:13 +03:00
Istvan Csomortani 5294e238d2 axi_ad9250: Port redeclaration as a wire is not allowed 2017-04-20 10:50:21 +03:00
Istvan Csomortani 6ab8624a06 axi_ad9625: Port redeclaration as a wire is not allowed 2017-04-20 10:49:24 +03:00
Lars-Peter Clausen 9f55a703cc axi_dmac: post_propagate(): Handle mappings with multiple address segments
When a mapping has multiple address segments we need to consider all of
them to calculate the required address width.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-19 13:47:02 +02:00
Lars-Peter Clausen 5084e4a8f7 axi_dmac: post_propagate(): Handle address segments with offsets
The address width needs to be large enough to be able to address the
largest possible address. This means the in addition to the address segment
range the specified offset also needs to be considered to calculate the
address width.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-19 13:47:02 +02:00
Istvan Csomortani db0cd63ed3 axi_ad9361: Fix Warning[Synth 8-2611]
In Verilog-2001 standard, redeclaration of an output port as a wire
is not allowed.
2017-04-19 13:52:13 +03:00