Because the inferface signals which pass through the eval board's
Arduino connector are connected to level shifters the design
will not work at the maximum clk frequency of 48MHz. The maximum
tested frequency is 24MHz.
Address size and memory ranges are automatically computed by the
external storage interfacing IP (util_hbm) based on the storage size and
base address so this parameter is redundant.
The internal bypass FIFO has poor timing performance,
when using HBM data can be passed always through the external memory
without storage length constraints, so no need for the internal bypass FIFO.
Make the storage type over writable so it can be set specifically
to carriers.
Address width of external memory AXI master is calculated in the
interfacing core (util_hbm) so that parameters is removed.
The HBM interfacing core requires a 450MHz clock, make it part of the
base design.
The clock can't be obtained from the DDR controller so a clock wizard is
used instead.
Deprecate unused parameters.
Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for
now. However in the future we might want to add support for non pow2
sizes so register map is not changed.
Change transfer length to -1 value to spare logic.
Change FIFO interface to AXIS to have backpressure, this allows the
implementation of data movement logic in the storage unit and let the
FSM handle high level control an synchronization and control the storage
unit through a control interface.
Refactor FSM to have preparation states where slow storages can be
configured and started ahead of the data handling.
Make bypasss FIFO optional since in some cases causes timing failures
due the missing output register of the memory. This can be targeted in
a later commit.
Hook up underflow/overflow to regmap useful in case of external memory
where rate drops due misconfiguration can be detected.
Cleanup for verilator.
Scripting:
Add HBM and DDR external memory support using util_hbm IP
Replace asym_block_ram with util_do_ram IP
Remove contraints related to quartus version so that
cn0506_mii and cn0506_rgmii on arria10 to be built
with default quartus version.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
There are no external termination resistors on the VCU118 and VCU128 for
the SGMII clock lines.
The board files of the VCU118 enables them, but this was not reflected in the
constraint files.
For VCU128 the clocking is similar, even if diff terms are not set in the
board files we should have a consistent approach with the VCU118.
There are no external termination resistors on the VCU118 for the SGMII
clock lines. The board files enables them, but this was not reflected in the
constraint files.
In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset or misconfigured. This will stop the clock generators from getting
a clock prior removing the reset of the XCVR. The XCVR has a requirement
of running user clock while removing the reset. The correct sequence must be :
Enable device clocks (user clock)
Remove the reset from the XCVR
In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset. This will stop the clock generators from getting a clock prior
removing the reset of the XCVR. The XCVR has a requirement of running
user clock while removing the reset. The correct sequence must be :
Enable device clocks (user clock)
Remove the reset from the XCVR
Reset CPACK from ADC TPL so during armed capture clear the cpack to avoid
capturing old samples.
Reset UNPACK with TPL to clear upack during armed transfers to avoid
sending old data.
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
Add the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
- allow specifying the name of Axi Lite interface from the peripheral were to connect the control bus
- some DDR controllers have an Axi Lite control interface, this creates
a second address segment which causes issues, differentiate the memory
segment from control registers segment
Vivado cannot nest multiple block designs than two layers. This makes
replication of designs difficult.
Create a hierarchy around the Versal transceiver that includes also the
converters, this type of interface would match the util_adxcvr
interface.
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
Laszlo Nagy
Stanca Pop
sergiu arpadi
Filip Gherman
Morten Jensen
PopPaul2021
David Winter
Adrian Costina
stefan.raus
LIacob106
AndreiGrozav
Ionut Podgoreanu
alin724
Dan Hotoleanu
Iulia Moldovan
Laszlo Nagy