Commit Graph

23 Commits (88f48cba619f281fc2b2f4102ad309391e9fa5ab)

Author SHA1 Message Date
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines
Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
Laszlo Nagy 31318cf311 all/system_top.v: drive unused gpio inputs with zero
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.

Connect these lines to zero instead.
2018-08-10 17:00:11 +03:00
Laszlo Nagy fa7c85a9eb all: Drive undriven input signals, complete interface
- connect unused GPIO inputs to loopback
- connect unconnected inputs to zero
- complete interface for system_wrapper instantiated in all system_top

fixes incomplet portlist WARNING [Synth 8-350]
fixes undriven inputs WARNING [Synth 8-3295]

The change excludes the generated system.v and Xilinx files.
2018-08-10 17:00:11 +03:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Lars-Peter Clausen ce8bcfd192 fmcjesdadc1: Remove wire that is a redeclaration of a port
Fixes the following warning:
	[Synth 8-2611] redeclaration of ansi port rx_sysref is not allowed

This is a leftover of commit 1c23cf4621 ("all: Update verilog files to
verilog-2001").

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-16 13:32:26 +01:00
Lars-Peter Clausen debca3a153 fmcjesdadc1: vc707: Remove unsed mb_intrs signal
The mb_intrs signal is never driven, it is a leftover of an earlier version
of the file, remove it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:38:25 +02:00
Lars-Peter Clausen 0360e8587e Connect JESD204 interrupts
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Istvan Csomortani f003b5b35a fmcjesdadc1: Reduce SYSREF period 2017-01-12 16:10:45 +02:00
Istvan Csomortani 8d799d0316 fmcjesdadc1: Intergrate ad_sysref_gen into project 2016-12-19 13:37:29 +00:00
Istvan Csomortani a54092c9bb fmcjesdadc1: Update projects to xcvr framework
This commit contains modifications for Xilinx only
2016-11-10 10:59:52 +02:00
Adrian Costina 7f9c526683 fmcjesdadc1: VC707 update project 2015-09-24 19:50:14 +03:00
Adrian Costina 8fc0e0e62d fmcjesdadc1: Fixed vc707 ethernet connections 2015-06-16 16:27:09 +03:00
Rejeesh Kutty a6cae6b477 iobuf: do is a system verilog keyword 2015-05-21 14:06:17 -04:00
Adrian Costina 11379939d0 fmcjesdadc1: VC707, Updated project to the latest framework 2015-03-30 18:08:19 +03:00
Istvan Csomortani 84f8377beb fmcjedadc1_vc707: Add support for linear flash interface 2014-11-21 19:19:21 +02:00
Istvan Csomortani e8546b9c3b fmcjesdadc1: Update interrupts for KC705 and VC707 2014-11-21 19:18:30 +02:00
Istvan Csomortani 2ce7695bf7 fmcjesdadc1: Initial commit of VC707 version 2014-09-01 18:47:01 +03:00