The derived clocks of the zynqmp core are not calculated correctly due
rounding issues, instead of 100MHz the value of 99999001 is received
causing warnings during system validation.
This can be fixed/worked around with the proper reference clock
definition.
For all the Xilinx base design, define three global clock nets, which
are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk
and $sys_iodelay_clk.
These clock nets are connected to different clock sources depending of
the FPGA architecture used on the carrier. In general the following
frequencies are used:
- sys_cpu_clk - 100MHz
- sys_dma_clk - 200MHz or 250Mhz
- sys_iodelay_clk - 200MHz or 500Mhz
- remove interrupts from system_top
- for all suported carriers:
- remove all interrupt bd pins
- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
Laszlo Nagy
Arpadi
Istvan Csomortani
AndreiGrozav
Nick Pillitteri
Rejeesh Kutty