Commit Graph

68 Commits (88f48cba619f281fc2b2f4102ad309391e9fa5ab)

Author SHA1 Message Date
Adrian Costina f5809b8817 adrv9371x: a10soc, added adcfifos; connected the new reset to all peripherals; used the new f2sdram1 port 2016-09-24 10:09:05 +03:00
Adrian Costina 521c41ce32 adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier 2016-09-08 11:44:45 +03:00
Adrian Costina d18f6aa816 adrv9371x: A10GX, added adcfifo
- connected dac dma to 133 MHz clock
- set explicit clock rate to xcvr reference clock bridge
2016-08-26 14:46:48 +03:00
Adrian Costina 215edb11c6 adrv9371: A10GX, updated design
- disable reconfiguration for RX transceivers and enabled the reconfiguration for TX transceiver. They cannot be enabled at the same time at this point
- update FIFO SIZE to 16 for all DMAs
- updated memory connections to 256 bit and moved clock connection to 133 MHz, for all DMAs.
2016-08-23 18:25:48 +03:00
Adrian Costina 270f8a6bbe adrv9371x: Updated project common 2016-08-22 16:58:21 +03:00
Adrian Costina 41203d07e9 adrv9371x: A10GX, update SPI connection 2016-08-18 17:42:27 +03:00
dbogdan 03c83b59bf adrv9371x/a10soc: Export axi_ad9371_s and xcvr_reconfig_avmm 2016-08-17 19:03:53 +03:00
Adrian Costina 5c27ccd1fa adrv9371x: Added common qsys tcl 2016-08-16 15:34:10 +03:00
dbogdan 4658686ae1 adrv9371x/a10soc: Misc changes for being able to run Linux 2016-08-16 11:56:25 +03:00
Istvan Csomortani 2e80dec513 adrv9371x/zc706: Update project with the new axi_dacfifo 2016-06-22 12:33:47 +03:00
Rejeesh Kutty 3351ff607e adrv9371x- need to investigate merge with avalon 2016-06-02 16:22:53 -04:00
Rejeesh Kutty a958ef27da adrv9371- qsys updates 2016-06-01 13:48:51 -04:00
Rejeesh Kutty af45acfcb9 ad9371- qsys updates 2016-06-01 13:48:51 -04:00
Istvan Csomortani 32d46389f2 adrv9371x: Move GTs AXI interface to HP3
If the VDMA and the GTs AXI are connected to the same HP port, the
HDMI won't work on full resolution (1080p). Care should be taken, this can
affect the receive and observation paths (both are connected to HP2).
2016-05-27 14:13:55 +03:00
Istvan Csomortani b452a8e2d4 adrv9371x: Connect bypass and data underflow 2016-05-27 14:13:55 +03:00
Istvan Csomortani 3859cba186 adrv9371x/zc706: Add PL_DDR FIFO to the design 2016-05-27 14:13:55 +03:00
Rejeesh Kutty 0d1c4d232e a10soc- updates-1 2016-05-20 16:14:57 -04:00
Rejeesh Kutty f92e8509bb adrv9371x- added 2016-05-20 11:46:25 -04:00