Iacob_Liviu
482f0489a3
scripts: Merge adi_env.tcl into a single file
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Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Iulia Moldovan
961ebe0cc2
projects: Update .v files according to guideline
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Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Adrian Costina
d40db9e204
adrv9009zu11eg: Added additional GPIOs and CS to the GPIO expander
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This should integrate seamlessly with SYNCHRONA14
2022-04-01 10:24:04 +03:00
PopPaul2021
c71e5de928
zcu102: ad_fmclidar1_ebz, fmcomms5, fmcomms8 ( #811 )
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adrv2crr_fmc: adrv9009zu11eg
adrv2crr_xmicrowave: adrv9009zu11eg
The IBUFGDS primitive is deprecated in UltraScale devices.
2021-11-22 08:09:46 +02:00
Adrian Costina
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
Adrian Costina
4cf53f373b
Revert "adrv9009zu11eg: Integrate data_offload"
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This reverts commit 78999e154e
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The integration wasn't properly tested
2021-08-19 21:43:09 +03:00
Istvan Csomortani
78999e154e
adrv9009zu11eg: Integrate data_offload
2021-08-06 11:55:24 +03:00
Sergiu Arpadi
a1773c661c
adrv9009zu11eg_crr: Update spi
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Add two more CS signals to P25 connector
2021-03-10 10:53:11 +02:00
Sergiu Arpadi
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
sergiu arpadi
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
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Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
Istvan Csomortani
e41ba7f6f5
adrv9009zu11eg: Use adi_project_create instead of adi_project
2021-01-15 15:26:43 +02:00
Istvan Csomortani
2799777657
adrv9009zu11eg/adrv2crr_fmc: Fix hmc7044_car_gpio connections
2020-11-11 07:07:29 -05:00
Adrian Costina
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
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Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
Sergiu Arpadi
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
Adrian Costina
c4b94fc564
adrv9009zu11eg: Add S JESD204 parameter for the projects
2020-02-18 11:19:02 +02:00
Adrian Costina
645696e5b4
adrv9009zu11eg: Extend SPI connection to the PL HD PINS expansion
2020-02-18 11:19:02 +02:00
Adrian Costina
09ad67bfd7
adrv9009zu11eg: Make the project more parametrizable
2019-12-04 14:59:18 +02:00
Adrian Costina
0cb5c0bdaf
adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency
2019-11-27 16:27:44 +02:00
Adrian Costina
dfe3258a4f
adrv9009zu11eg: Add axi_sysid
2019-11-19 10:29:57 +02:00
Adrian Costina
a589a2c7eb
adrv9009_zu11eg_som: Change design partitioning
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Create a structure similar with ADRV936x projects
2019-11-14 15:25:23 +02:00