Istvan Csomortani
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88e0cfec42
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axi_dacfifo: The AXI read and write have the same properties
AXI read and AXI write channel have the same SIZE and LENGTH.
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2016-05-27 14:13:55 +03:00 |
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Istvan Csomortani
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aca3038919
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axi_dacfifo: No overflow for DAC
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2016-05-27 14:13:55 +03:00 |
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Istvan Csomortani
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81ade7f26c
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axi_dacfifo: Fix resets
DMA side: axi_resetn is used to reset the address counters
DAC side: GT tx_rst is used to reset the last_address register
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2016-05-27 14:13:55 +03:00 |
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Istvan Csomortani
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578376c8fe
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axi_dacfifo: Add bypass logic
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2016-05-27 14:13:55 +03:00 |
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Istvan Csomortani
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e855ef38f4
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axi_dacfifo: Initial commit
AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
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2016-04-19 11:28:33 +03:00 |
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Istvan Csomortani
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896c734792
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Revert "foobar"
This reverts commit a3cb8cac45.
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2016-03-18 13:23:02 +02:00 |
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Istvan Csomortani
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a3cb8cac45
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foobar
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2016-03-18 11:51:13 +02:00 |