Lars-Peter Clausen
b206f8f37a
m2k: Disable AD9963 core RX datapath again
...
The RX datapath has a lot of things (IQ correction, DC filter, ...) that
take up a lot of space which are all not really needed in this project. So
disable the RX datapath.
It was previously enabled because the ad9963 core did not perform
sign-extension on the ADC data signal when the datapath was disabled. But
this has now been addressed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen
c1ba57f808
m2k: Rework clocking domains
...
At the moment the register map fabric and DMA system memory side are
clocked by the 100MHz sys_cpu_clk. While this works fine that is a lot
faster than the clock has to run. There are only a few 100 register map
accesses per seconds at most and they are not on timing critical paths. The
penalty from clocking them at a lower rate is negligible for the overall
system performance.
The maximum clock rate for the DMAs is determined by the throughput
requirements. This is 200 Mbytes/s for the logic analyzer, pattern
generator and each of the DAC DMAs and 400 Mbytes/s for the ADC DMA.
The DMA datapath width is 64-bit so the required clock rates are 25MHz and
50MHz respectively. Some headroom is required to accommodate for occasional
bubble cycles on the data bus and the difference in reference clocks for
the converter and processing system.
The sys_cpu_clk is reduced to 27.8MHz which is fast enough for all but the
ADC DMA. For the ADC DMA a new clock domain running at 55.6 MHz is
introduced.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen
2eaf931e07
m2k: Replace logic analyzer MMCM
...
The MMCM generating the logic analyzer clock unfortunately consumes a
disproportionately large amount of power compared to the rest of the
design.
Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs.
The IO PLL is running anyway so the power requirement is much lower.
For the time being this means we loose the ability to source the clock from
an external pin. But that feature is not supported by software at the
moment anyway. We'll bring it eventually when required.
This changes reduces power consumption by roughly 100mW.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen
e616c8da0b
m2k: Remove channel pack core for now
...
We always have both ADC channels enabled and the cpack core takes up a fair
amount of space, so remove it for now. Might come back later when we really
need it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Adrian Costina
efa2d0c006
m2k: Connected adc/dac resets to decimation/interpolation cores
2017-04-18 12:17:39 +02:00
Adrian Costina
500112f79b
m2k: Renamed l_clk to adc_clk and rst to adc_rst
2017-04-18 12:17:39 +02:00
Adrian Costina
6a49aefb6c
m2k: Updated project to use new tx path with serdes
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen
b58a5c37eb
m2k: Reduce AXI interconnect utilization
...
Use the new axi_rd_wr_combiner module to ... the read and write DMA
interfaces into a single interface. This allows the AXI interconnect
completely optimize itself away and reduce the overall resource utilization
of the project.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Adrian Costina
71394ee465
kcu105: ip automatic version update
2017-04-18 11:59:54 +03:00
Adrian Costina
942d69a30c
Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU
2017-04-18 10:57:16 +03:00
Adrian Costina
8e0c87e089
pluto: cleaned up some warnings
2017-04-18 10:34:13 +03:00
Adrian Costina
f3c0be0868
motcon2_fmc: cleaned up some warnings
2017-04-18 10:33:13 +03:00
Adrian Costina
6e14cdb5f4
cftl_std: cleaned up some warnings
2017-04-18 10:32:28 +03:00
Adrian Costina
d585d65692
cftl_cip: cleaned up some warnings
2017-04-18 10:29:20 +03:00
Adrian Costina
20672a3a8b
mitx045: ip automatic version update
2017-04-14 17:46:25 +03:00
Adrian Costina
954037a716
microzed: ip automatic version update
2017-04-14 17:24:24 +03:00
Adrian Costina
ebc04bcd9c
usdrx1: ip automatic version update
2017-04-14 17:16:35 +03:00
Adrian Costina
24b797f1a6
motcon2: ip automatic version update
2017-04-14 17:11:08 +03:00
Adrian Costina
4981e6e525
usb_fx3: ip automatic version update
2017-04-14 16:55:30 +03:00
Adrian Costina
c419b0042b
pluto: ip automatic version update
2017-04-14 16:55:07 +03:00
Adrian Costina
79174422b6
imageon: ip automatic version update
2017-04-14 16:54:42 +03:00
Adrian Costina
4bda0c3a1a
cftl_cip: ip automatic version update
2017-04-14 16:54:07 +03:00
Adrian Costina
afe8b071a3
cftl_std: ip automatic version update
2017-04-14 16:53:10 +03:00
Istvan Csomortani
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
AndreiGrozav
04a4001dba
Ip automatic version update: fmcadc2, fmcadc5
2017-04-12 19:03:16 +03:00
AndreiGrozav
627f78ec19
Ip automatic version update: common/board
...
- vc707
- zc702
- zed
2017-04-12 19:03:16 +03:00
Rejeesh Kutty
6d2b3bc1c7
adi_project- try something simple first
2017-04-11 14:27:35 -04:00
Rejeesh Kutty
1d9a8a24dc
adi_board- create_bd_cell replacement
2017-04-11 14:26:02 -04:00
AndreiGrozav
bc9483c5a2
Ip automatic version: Update ad*/common/ad*_bd.tcl
...
ad6676evb/common/ad6676evb_bd.tcl
ad7616_sdz/common/ad7616_bd.tcl
ad7768evb/common/ad7768evb_bd.tcl
ad9265_fmc/common/ad9265_bd.tcl
ad9434_fmc/common/ad9434_bd.tcl
ad9467_fmc/common/ad9467_bd.tcl
ad9739a_fmc/common/ad9739a_fmc_bd.tcl
adrv9371x/common/adrv9371x_bd.tcl
adv7511/common/adv7511_bd.tcl
fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 18:52:37 +03:00
Rejeesh Kutty
454e6c0382
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 13:04:53 -04:00
Rejeesh Kutty
2535165461
xilinx- ad-ip-instance & ad-ip-parameter
2017-04-06 13:04:19 -04:00
Rejeesh Kutty
80f93e6a31
zc706- ad-ip-instance & ad-ip-parameter
2017-04-06 13:03:22 -04:00
Rejeesh Kutty
820874ef93
adi_board- add auto ip version handling
2017-04-06 13:02:17 -04:00
Lars-Peter Clausen
e04793b6eb
m2k: standalone: Assign 0 to unused GPIO inputs
...
To avoid warnings from the tools assign 0 to the unused GPIO inputs.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 11:16:25 +02:00
Rejeesh Kutty
8eb1dd0a8b
adrv9371x/altera- xilinx/chip-select consistency
2017-03-29 12:59:09 -04:00
Lars-Peter Clausen
24a7d8ea9d
m2k: Remove redundant s_axi_{aclk,aresetn} assignment
...
ad_cpu_interconnect will make sure to connect the clock and the reset of
the AXI interface. Remove the redundant manual assignments.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-28 11:14:48 +02:00
Rejeesh Kutty
deb8635854
adrv9371x/altera- gpio equivalency fix
2017-03-27 16:37:55 -04:00
Rejeesh Kutty
8f1564a9c4
adrv9371x/a10gx- gpio matching
2017-03-27 13:51:45 -04:00
Rejeesh Kutty
ae0f4672b2
daq1/a10gx- fix project to compile
2017-03-23 09:46:40 -04:00
Rejeesh Kutty
cc6bf53d98
adrv9371x/a10soc- altera reset synchronizer false path?
2017-03-23 09:46:40 -04:00
Adrian Costina
968d94603e
fmcjesdadc1: Update xcvr configuration to the default one used for this board
2017-03-23 11:31:00 +02:00
Rejeesh Kutty
4a275302a0
a5soc- add ddr3 location assignments
2017-03-22 10:12:34 -04:00
Rejeesh Kutty
7e87ecae22
altera/a10gx- daq1/fmcomms2 fix typos
2017-03-22 09:48:02 -04:00
Rejeesh Kutty
b3f06af77a
altera srf files do not work
2017-03-22 09:25:50 -04:00
Rejeesh Kutty
66a5d44a18
a5gte- add constraints for tq
2017-03-21 10:53:31 -04:00
Rejeesh Kutty
2e22ce3b62
a10gx- ignore preliminary timing model warnings
2017-03-21 10:52:28 -04:00
Rejeesh Kutty
d84e34fe5f
arradio/c5soc- reset false path for vga dma
2017-03-21 10:15:38 -04:00
Rejeesh Kutty
8063ba2b66
make updates
2017-03-20 16:05:18 -04:00
Rejeesh Kutty
c7351f3ce3
arradio/c5soc- remove qsys files
2017-03-20 15:56:07 -04:00
Rejeesh Kutty
589e6b53d8
arradio/c5soc- qsys-script flow
2017-03-20 15:42:33 -04:00
Rejeesh Kutty
b39fecadd9
altera- ignore preliminary timing messages
2017-03-20 12:48:53 -04:00
Rejeesh Kutty
7dfa8c599f
arradio/c5soc- updated to new framework/16.0
2017-03-20 12:15:18 -04:00
Rejeesh Kutty
12f44ccbcc
arradio/c5soc- critical warnings fix
2017-03-20 12:14:21 -04:00
Rejeesh Kutty
9b6dd27c23
ad9361- delay initialization
2017-03-15 12:06:59 -04:00
Adrian Costina
09bcecb6ed
m2k: Simplify DMA connection to HP1
2017-03-15 15:11:30 +02:00
Adrian Costina
2a9b3cea09
m2k: Changed the way DMAs connect to the PS7 DDR, to optimize resources use
2017-03-14 13:57:50 +02:00
Adrian Costina
f7c2bd943b
m2k: Enable AD9963 adc data path processing.
...
- part of the path is the sign extension module. Without it, the triggering doesn't work correctly
2017-03-13 23:18:29 +02:00
Rejeesh Kutty
c3c8c366d3
axi_ad9361- add receive init delay
2017-03-13 16:28:53 -04:00
Rejeesh Kutty
dac75f79ab
fmcomms5/usrpe31x- add iodelay report
2017-03-10 13:38:27 -05:00
Rejeesh Kutty
1b3f752c3d
pzsdr1/pzsdr2/pluto- add iodelay report
2017-03-10 12:55:22 -05:00
Rejeesh Kutty
0ae79ca7ac
move/rename - delay script belongs to ad9361
2017-03-10 12:44:32 -05:00
AndreiGrozav
e736504e0f
fmcjesdadc1, usdrx1: Using the same clock in rx_data path
2017-03-10 14:26:51 +02:00
AndreiGrozav
d08d1d5a1b
adrv9371x ,daq3, fmcomms7, fmcomms11: add dac_fifo missing reset connection
2017-03-10 14:20:42 +02:00
Rejeesh Kutty
452e5e5ce0
fmcomms2- add delay reporting for iodelay
2017-03-09 15:29:15 -05:00
Rejeesh Kutty
8bdfbe2b0a
fmcomms2- report delays
2017-03-09 15:21:42 -05:00
AndreiGrozav
7e5d8664ad
fmcjesdadc1_a5gt: rx_data pins are all associated to the same clock
2017-03-09 08:57:03 +02:00
AndreiGrozav
0e002f2f31
daq3_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-09 08:50:55 +02:00
Istvan Csomortani
191669ad28
daq2_common: Fix the dac_rst for DAC FIFO
2017-03-07 16:13:46 +02:00
Rejeesh Kutty
fc8af6903f
pzsdr2/ccfmc- add rf input protection
2017-03-06 16:19:55 -05:00
Rejeesh Kutty
3fa9a30f0e
a10soc/plddr4- lower mem clk to meet timing
2017-03-06 14:12:25 -05:00
Rejeesh Kutty
38a27d02f6
a10soc/plddr4- differential refclk
2017-03-06 14:11:36 -05:00
Rejeesh Kutty
936c441763
adrv9371x- dacfifo bypass-gpio control
2017-03-06 10:35:09 -05:00
Rejeesh Kutty
762276a880
adrv9371x- dacfifo changes
2017-03-06 10:33:52 -05:00
Istvan Csomortani
4a6fe54fcf
daq2_common: Update common scripts
...
Add new port connection for util_dacfifo
2017-03-03 18:49:10 +02:00
Rejeesh Kutty
ec89b1a45f
altera/adrv9371x- add dacfifo
2017-03-01 15:52:07 -05:00
Rejeesh Kutty
bc6a09c828
adrv9371x/a10soc- dacfifo added
2017-03-01 15:35:04 -05:00
AndreiGrozav
5b5c0dde99
ad6676evb: Set default xcvr parameters to common design
2017-03-01 11:32:17 +02:00
AndreiGrozav
b78e9d8c27
daq2_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-01 11:32:17 +02:00
AndreiGrozav
0cc5130c9a
adrv9371x: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-01 11:32:17 +02:00
AndreiGrozav
c1be17a3af
Altera a10 devices: disable warnings regarding unused channels
2017-03-01 11:32:17 +02:00
AndreiGrozav
dc168f41fe
adrv9371_a10soc: Fixed port assignments
2017-03-01 11:32:17 +02:00
Rejeesh Kutty
aad41039bd
a10soc- plddr4 settings
2017-02-28 13:36:28 -05:00
Adrian Costina
59dda01419
m2k: Disabled DDS cores for the generic project
2017-02-28 10:10:28 +02:00
Rejeesh Kutty
fb4a583613
projects/system_bd- adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
Rejeesh Kutty
6b1a8852a9
dacfifo- bypass port name change
2017-02-27 16:06:39 -05:00
Rejeesh Kutty
19c7b5d340
fmcadc5- move adc fifo settings to system-board
2017-02-27 16:06:39 -05:00
Rejeesh Kutty
c1aac4a9fb
common: adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
Adrian Costina
545e458997
m2k: Standalone, ignored critical warning for contraints that should only be applied at the implementation stage
2017-02-27 14:17:29 +02:00
Adrian Costina
eda585f0e4
m2k: Connected data[0] and trigger[0] pins to the logic analyzer clock generator input 2
2017-02-27 14:16:32 +02:00
Adrian Costina
908da60ab6
m2k: zed, changed constraints so they are the same with the ZED default configuration
...
- the voltage can be physically changed between 1.8V, 2.5V and 3.3V
2017-02-27 14:13:34 +02:00
Istvan Csomortani
0059c907ea
adrv9371: Drive the TX DMA interface with sys_dma_clk
2017-02-24 15:50:12 +02:00
Istvan Csomortani
ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
Istvan Csomortani
1fce57f6c3
axi_dacfifo: Redesign the bypass functionality
2017-02-23 17:32:31 +02:00
Rejeesh Kutty
c598e84258
remove processing order (no clock def dependency)
2017-02-22 16:02:08 -05:00
Rejeesh Kutty
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
Rejeesh Kutty
b00dc4b195
plddr3- change to board files
2017-02-22 15:22:50 -05:00
Rejeesh Kutty
89b49d2f67
fifo- as board files
2017-02-22 15:18:50 -05:00
Rejeesh Kutty
879ed64bb6
compression flag changes
2017-02-22 15:15:53 -05:00
Rejeesh Kutty
8a5e2ff46e
sys_wfifo- removed
2017-02-22 15:13:18 -05:00
Rejeesh Kutty
754ac6a403
w/r-fifo- removed
2017-02-22 15:10:06 -05:00