c4b4bdc415
daq2/a10gx- constraints remove 16.0
2017-05-16 10:09:42 -04:00
cfcb269d38
a10gx- change ddr to 1G
2017-05-15 09:32:36 -04:00
63b701ccab
altera- add version check
2017-05-12 15:13:29 -04:00
ebeebdddf0
altera- infer latest versions
2017-05-12 13:40:14 -04:00
c728299e71
altera- default to latest version
2017-05-12 13:25:17 -04:00
ecfa15bfce
version check- change to critical warning
2017-05-12 09:51:48 -04:00
039ae9ae92
fmcadc5- syntax/port name fixes
2017-05-10 16:30:15 -04:00
6a0a2e4661
hdlmake.pl updates
2017-05-10 14:35:06 -04:00
74c44cf830
axi_fmcadc5- remove pack-driver is too late
2017-05-10 14:33:56 -04:00
0e5a24ee7c
axi_fmcadc5_sync- raw inputs & constraint fixes
2017-05-08 10:30:51 -04:00
6387b53266
ad77681evb: Initial commit
2017-05-04 12:19:11 +03:00
ef97c1e375
adrv9371x/a10soc: Fix constraints
...
Signed-off-by: Istvan Csomortani <istvan.csomortani@analog.com>
2017-05-02 14:37:11 +03:00
f0bc3e20ef
zcu102: Automatic IP version update fix
2017-05-02 12:52:43 +03:00
cd8f4f23be
zcu102: Automatic IP version update
2017-05-02 12:30:00 +03:00
d6b09602ed
usrpe31x: Automatic IP version update
2017-05-02 12:27:57 +03:00
485c810c2c
pzsdr*: Automatic IP version update
2017-05-02 11:43:32 +03:00
b3ce821311
change pl ddr clock to 1G
2017-05-01 09:35:10 -04:00
d29f420ffa
axi_fmcadc5_sync: add a calibration signal generation
2017-04-28 11:13:24 -04:00
7a53b99b8b
daq2: zc706: Increase DAC FIFO size
...
Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is
quite a limiting size for practical applications. Increase the size to 1MB
to allow loading larger waveforms.
In this configuration the DAC FIFO will use half of the available BRAM
cells in the FPGA. This still leaves quite a few BRAMs available for
user application logic added to the design. If a user design should run out
of BRAMs nevertheless they can reduce the FIFO size, if not required by the
application, to free up some cells.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-28 12:29:01 +02:00
f6eea23f5e
adaq7980: Update tcl command for IP configuration
2017-04-28 10:12:33 +03:00
353d1d44da
ad5766_sdz: Update tcl commands for IP configuration
2017-04-28 10:12:05 +03:00
956753ca9c
hdlmake- updates
2017-04-27 15:11:01 -04:00
68fc5c89a7
fmcadc5- remove stand alone psync
2017-04-27 15:09:56 -04:00
75c7525c60
fmcadc5- remove psync module
2017-04-27 13:29:06 -04:00
2027c8427c
adi_boadr- disconnect and remove unused ports
2017-04-27 13:26:17 -04:00
902eaaaf4c
fmcadc5- sync updates
2017-04-27 13:26:17 -04:00
0442e7d404
util_adxcvr: Fix parameter setup at instantiation
...
If a parameter value is defined as a string binary (e.g. "001001000000"),
it can confuse the tool, and the value may be used as a decimal number.
To prevent this issue and to improve readability converting all the binary
constants into hexadecimal.
2017-04-27 15:35:39 +03:00
8aa8d3a0e5
ad5766_sdz/zed: Fix i_iobuf_reset width
2017-04-27 11:28:26 +03:00
4836aa2179
adaq7980/zed: Update Makefile
2017-04-27 11:28:25 +03:00
fbccb377cc
adaq7980: Add an trigger generator for SPI offload
2017-04-27 11:28:23 +03:00
63cab50872
adaq7980_sdz: Initial commit
...
The device is interfaced with a SPI Engine, the PD lines are controlled
by GPIOs.
2017-04-27 11:28:23 +03:00
ccc4aac505
ad5766_sdz: Fix the PIN assignment
2017-04-27 11:27:34 +03:00
8213d8a916
cn0363: Update block design
...
Configure the interconnect and offload modules inorder to activate
its interfaces. In the past, these interfaces did not have any
parameter dependencies, so this configuration were not required.
2017-04-27 11:27:33 +03:00
a6146393be
ad5766_sdz: Fix DMA data path
2017-04-27 11:22:32 +03:00
a2c20551a2
axi_ad5766: Add Makefiles for the core
2017-04-27 11:22:31 +03:00
f5fba79a08
ad5766_zed: Add an IOBUF to the reset line
2017-04-27 11:21:14 +03:00
9de0fe56d9
ad5766: Integrate the new axi_ad5766 into the project
2017-04-27 11:21:14 +03:00
d177827224
ad5766_sdz : Fix SPI interface connection
2017-04-27 11:16:23 +03:00
225d133a68
ad5766_sdz: Initial commit
2017-04-27 11:12:45 +03:00
cfd4e006b3
hdlmake updates
2017-04-25 15:46:26 -04:00
8fba8295f0
fmcadc5- hdl sync handling
2017-04-25 15:44:40 -04:00
68bb7ffa40
adi_board- keep port delete simple
2017-04-25 15:44:03 -04:00
8eb65186e9
cn0363: Reorder the configuration settings of the fir filters
...
It seems that there are some dependencies between the fir compiler
cores parameters. With the old order of the parameter settings,
the tool throws the following warning:
CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES
does not match between /processing/sequencer/i_q_filtered(4)
and /processing/lpf/M_AXIS_DATA(5)
2017-04-25 17:40:09 +03:00
a6457cb54f
m2k:standalone, remove power optimizations as they are performed manually
...
- testing shows that the actual power consumtion is a bit less with them turned off
2017-04-25 10:09:55 +03:00
b92703b59f
daq2: Fix typo
2017-04-24 15:44:45 +03:00
0cfef974a6
cn0363: Fix typos and mistakes made in 0737183
2017-04-24 12:43:33 +03:00
b9bc85dd1a
daq2/zcu102: Update tcl command for IP configuration
2017-04-24 11:51:12 +03:00
871cfa7e5b
daq2/kcu105: Update tcl command for IP configuration
2017-04-24 11:50:35 +03:00
49f096dc71
daq1: Fix typo
2017-04-24 11:49:08 +03:00
4e77acf282
adv7511/kcu105: Update tcl command for IP configuration
2017-04-24 11:48:33 +03:00
Rejeesh Kutty
Istvan Csomortani
AndreiGrozav
Lars-Peter Clausen
Dragos Bogdan
Adrian Costina