6548bcd71f
axi_ip- constraints: add rst path
2015-06-04 10:53:13 -04:00
e02273781f
ad_rst- non lpm version
2015-06-04 10:53:12 -04:00
91b0f70972
library: remove drp cntrl
2015-06-02 09:58:57 -04:00
2b5abf74d7
util_upack: Show upack_valid only if the channel is activated
2015-06-02 11:36:06 +03:00
297e885981
library- drp moved to up-clock domain
2015-06-01 14:52:52 -04:00
e7470036bf
library- drp moved to up clock
2015-06-01 13:39:26 -04:00
c6ebab7393
library- drp moved to up clock
2015-06-01 13:39:26 -04:00
aa24c442f5
a10gx- no-ddr
2015-06-01 11:00:01 -04:00
d7b68c39ef
altera- sdc
2015-06-01 10:59:59 -04:00
2a0bdbebf2
altera- sdc
2015-06-01 10:59:58 -04:00
92fc0e050d
altera- common sdc
2015-06-01 10:59:57 -04:00
83df53d9bf
adc_common: Updated version because the delay registers have been changed
2015-05-25 17:18:14 +03:00
1ef83bd88b
axi_ad9671: Updated port names. Fixed synchronization of the rx_sof with the ad_jesd_align module, so that data valid is assigned correctly
2015-05-23 00:16:27 +03:00
660c84e01c
axi_ad9434 : Update the IO delay interface
2015-05-22 19:47:09 +03:00
0c6ef203c0
iobuf: do is a system-verilog keyword
2015-05-21 14:06:13 -04:00
dc2eeebf2f
upack: gen-name
2015-05-21 14:06:12 -04:00
5c6340e927
dmac: clock-typo
2015-05-21 14:06:11 -04:00
e05ff26406
ad9144: ddata-typo
2015-05-21 14:06:09 -04:00
8d78217f7b
ad9680: missing prot. ports
2015-05-21 14:06:08 -04:00
4c6a3afc88
ad9144: missing prot. ports
2015-05-21 14:06:06 -04:00
a059290cf5
Remove axi_ad7175
...
This core has been superseded by the SPI Engine framework in combination
with the axi_generic_adc core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
c53f8c15ee
Add CN0363 project
...
Add support for the CN0363 (colorimeter) board connected to the ZED board.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
d43ba44d0f
Add util_sigma_delta_spi peripheral
...
The util_sigma_delta_spi peripheral can be used to seperate the interleaved
SPI bus and DRDY signals for a ADC from the Analog Devices SigmaDelta
family.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
e6b58e8a20
Add SPI Engine framework
...
SPI Engine is a highly flexible and powerful SPI controller framework. It
consist out of multiple sub-modules which communicate over well defined
interfaces. This allows a high degree of flexibility and re-usability while
at the same time staying highly customizable and easily extensible.
Currently included are four components:
* SPI Engine execution module: The excution module is responsible for
handling the low-level physical interface SPI logic.
* SPI Engine AXI interface module: The AXI interface module allows
memory mapped acccess to a SPI bus control stream and can be used to
implement a software driver that controls the SPI bus.
* SPI Engine offload module: The offload module allows to store a
predefined SPI Engine command and data stream which will be send out
when a external trigger signal is asserted.
* SPI Engine interconnect module: The interconnect module allows to
combine multiple control streams into a single stream giving multiple
control modules access to a execution module.
For more information see: http://wiki.analog.com/resources/fpga/peripherals/spi_engine
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
a5b452cc27
Add axi_generic_adc core
...
The axi_generic_adc core is a simple core that doesn't do much more then
implementing the AXI ADC register map and routing the enable and overflow
signals to the farbic.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
033713ccb5
Add cordic demodulator module
...
The cordic_demod module takes in phase and data on s_axis interface then
performs a cordic demodulation and outputs the resulting I and Q component
data on the m_axis interface.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
cefbe3a0ff
scripts/adi_ip.tcl: Add option to specify reset interface direction
...
Allow to specify the direction of the reset signal for a interface, this is
useful if the core itself generates the reset signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
6b9906b22b
Refresh Makefiles
...
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
5ac7ebb8a3
axi_mc_*: Removed delay pins from up_adc_common
2015-05-21 14:03:58 +03:00
465f7dff88
library/util_jesd_align -added
2015-05-20 15:38:43 -04:00
9762c65868
library- jesd-align port name change
2015-05-20 14:25:21 -04:00
da0409b5a6
library- qsys components
2015-05-20 11:51:50 -04:00
9b425736ac
library: altera ip modifications
2015-05-20 10:41:21 -04:00
d48d3f4aa3
scripts/ip-alt- added
2015-05-20 09:11:18 -04:00
e918588a4b
library: remove axi-min-size parameter
2015-05-19 13:07:48 -04:00
4fb1be0672
ad9680: delay changes
2015-05-19 12:53:56 -04:00
af7afd7366
ad9671: delay changes
2015-05-19 12:53:56 -04:00
09a05fe9d8
ad9652: delay changes
2015-05-19 12:53:56 -04:00
13156593f8
ad9643: delay changes
2015-05-19 12:53:56 -04:00
c8d3c04a05
ad9625: delay changes
2015-05-19 12:53:56 -04:00
f53204f9f9
ad9467: delay changes
2015-05-19 12:53:56 -04:00
fe0ceb2530
delay-cntrl updates
2015-05-18 15:23:10 -04:00
304a202d67
delay-cntrl updates
2015-05-18 14:57:05 -04:00
2e257db109
delay-cntrl updates
2015-05-18 14:53:24 -04:00
0877c252ad
delay-cntrl changes
2015-05-18 14:28:20 -04:00
2bad47cf4f
delay-cntrl: up-clk, direct access + tx
2015-05-18 14:28:20 -04:00
6e047f78c6
delay-cntrl: up-clk, direct access + tx
2015-05-18 14:28:20 -04:00
2c1719095d
util_axis_resize: Changed _ip.tcl format to the standard format
2015-05-18 17:25:07 +03:00
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
...
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
a07d11c3e9
axi_ad9361_tdd: Define control bits for continuous receive/transmit
2015-05-14 17:21:32 +03:00
c9c05e21c2
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 16:34:06 +03:00
7c9bc40c75
axi_ad9361&TDD: Update TDD
...
+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
2015-05-13 14:03:01 +03:00
a1d680ee6b
ad9680- add hw tcl
2015-05-12 15:06:42 -04:00
833a3de6b5
ad9680- add hw tcl
2015-05-12 15:06:39 -04:00
48c769d431
ad9144- add hw tcl
2015-05-12 14:40:38 -04:00
553f89f59d
ad9144- add hw tcl
2015-05-12 14:39:57 -04:00
4553de3ffa
ad9361- align hold
2015-05-11 11:55:01 -04:00
9934cce5d2
util_dacfifo: Add CDC logic for dma_lastaddr register.
2015-05-11 12:20:46 +03:00
2e7135c3c2
axi_ad9361_tdd: Initial commit.
...
Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 12:20:44 +03:00
14e23b106c
axi_ad9361: changed device interface module for Altera to have the same inputs as the one for Xilinx
2015-05-08 17:43:10 +03:00
12ed393d39
ad9361- framing modifications
2015-05-07 15:13:18 -04:00
a68539edf1
ad9361- framing modifications
2015-05-07 15:13:17 -04:00
176a4a4b76
ad9361: add ddr-edgesel
2015-05-06 16:58:50 -04:00
a8534a9c02
ad9361: add ddr-edgesel
2015-05-06 16:58:49 -04:00
32f7e98afd
ad9361: add ddr-edgesel
2015-05-06 16:58:47 -04:00
670850183b
axi_hdmi_tx: Updated constraints as in fmcomms2/zc702 project they were not correctly applied
2015-05-06 18:53:19 +03:00
a7c96fdac8
util_dacfifo: General clean up of the IO, input/output data has the same width
2015-05-06 16:32:44 +03:00
0613dca0b7
axi_dmac: Move the 'axis_xlast' logic into the dest_axi_stream module
2015-05-06 16:10:28 +03:00
949abcdc8f
Makefile: Updated makefiles so that the project recipe does not depend on lib
2015-05-06 14:58:29 +03:00
65af205d6b
axi_dmac: Add axis_last control signal to the Master AXI Streaming interface
...
This control signal can be overwritten by the up_axis_xlast/up_axis_xlast_en bits, in order to create a single stream, which is contains multiple streams.
This can be use to fill up the DACFIFO module.
2015-05-06 13:54:31 +03:00
233cc111d2
util_pmod_adc: Used generated clock for the ADC SPI. Works by default at 6.25MHz
2015-05-05 23:33:13 +03:00
3517b6941c
adv7511:kcu105, axi_hdmi_tx, axi_spdif_tx constraints modified so they apply to ultrascale
2015-05-05 10:06:26 +03:00
707b285669
prcfg: bb def
2015-05-04 10:24:13 -04:00
be32715ab3
axi_adcfifo: Updated constraints
2015-04-30 14:23:24 +03:00
d623f77453
axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst.
...
Resets for both up clock domain and rx clock domain are needed in some projects
2015-04-30 12:07:36 +03:00
463c4d4d28
util_wfifo: Added constraint for the resetn path
2015-04-30 12:05:02 +03:00
392ba31a07
axi_hdmi_rx: Updated constraints
2015-04-30 12:04:15 +03:00
288b9cccff
Makefile: Added makefiles for imageon_loopback project. Updated axi_ad9152, util_gmii_to_rgmii, util_wfifo to include constraints file
2015-04-28 15:22:37 +03:00
a7a2d194e9
axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core
2015-04-28 15:04:18 +03:00
c36186f75a
axi_ad9643: Added adc_rst output
2015-04-28 14:52:24 +03:00
8ee3f64a65
axi_ad9265: Added adc_rst output
2015-04-28 14:51:14 +03:00
67c581cef8
util_wfifo: Updated to be used with adc_rst from the adc_clk clock domain
2015-04-28 14:50:00 +03:00
1ad87aa27c
util_wfifo: Added constraints
2015-04-27 11:19:56 +03:00
81d4e1d9b1
axi_clkgen: Updated constraints
2015-04-27 11:19:15 +03:00
d950f5ffcd
axi_ad9122: Updated constraints
2015-04-27 11:18:52 +03:00
9fba4cb2ef
util_dacfifo: Add support for Slave AXI stream interface.
...
The FIFO can be initialized through an AXI stream interface too.
2015-04-27 10:40:55 +03:00
3a02998e9a
axi_ad9152/axi_ad9152_ip.tcl: Fix typo
...
axi_ad9152_constr.v -> axi_ad9152_constr.xdc
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-24 09:41:43 +02:00
a9924e6401
util_gmii_to_rgmii: Added constraints
2015-04-23 16:53:57 +03:00
bd06bae8c2
library: Modified the adi_ip.tcl script
...
The constraints processing order changed to "late" instead of "early", in order for all the clocks in the system to be already created when the IP constraints are applied
2015-04-23 14:31:23 +03:00
a61a195e3f
Makefiles: Updated makefiles to add the new constraints as dependecies
2015-04-23 11:16:39 +03:00
d42c0bc431
axi_jesd_gt : Added CDC and reset constraints
2015-04-23 11:03:51 +03:00
1b4e6bdc80
axi_mc_speed : Added CDC and reset constraints
2015-04-23 10:50:49 +03:00
6d28d217f1
axi_mc_current_monitor: Added CDC and reset constraints
2015-04-23 10:49:43 +03:00
d0b2d531bc
axi_mc_constroller: Added CDC and reset constraints
2015-04-23 10:47:35 +03:00
d0571a912f
axi_hdmi_tx: Added CDC and reset constraints
2015-04-23 10:46:04 +03:00
cc7d9f9d54
axi_clkgen: Added CDC and reset constraints
2015-04-23 10:44:37 +03:00
d1558df625
axi_ad9739a: Added CDC and reset constraints
2015-04-23 10:42:27 +03:00
97dc7ea004
axi_ad9680: Added CDC and reset constraints
2015-04-23 10:40:41 +03:00
f1f8c14813
axi_ad9671: Added CDC and reset constraints
2015-04-23 10:39:11 +03:00
744a15a0ba
axi_ad9652: Added CDC and reset constraints
2015-04-23 10:37:15 +03:00
eca616a3ae
axi_ad9643: Added CDC and reset constraints
2015-04-23 10:35:12 +03:00
a62415b0ab
axi_ad9625: Added CDC and reset constraints
2015-04-23 10:33:51 +03:00
b4a09daf89
axi_ad9467: Added CDC and reset constraints
2015-04-23 10:30:33 +03:00
ac79c65b81
axi_ad9434: Added CDC and reset constraints
2015-04-23 10:28:46 +03:00
a6cb6b7672
axi_ad9265: Added CDC and reset constraints
2015-04-23 10:27:29 +03:00
08f19d489f
axi_ad9250: Added CDC and reset constraints
2015-04-23 10:25:19 +03:00
734fdab326
axi_ad9234: Added CDC and reset constraints
2015-04-23 10:23:22 +03:00
09f05cf8e9
axi_ad9152: Added CDC and reset constraints
2015-04-23 10:21:52 +03:00
3526145992
axi_ad9144: Added CDC and reset constraints
2015-04-23 10:19:43 +03:00
e7ce2b200d
axi_ad9122: Added CDC and reset constraints
2015-04-23 10:17:53 +03:00
691c54e0dd
axi_ad6676: Added CDC and reset constraints
2015-04-23 10:16:29 +03:00
7b073aaec1
axi_dmac: Always generate local interrupt for asynchronous interfaces
...
While the reset for the memory mapped AXI master is synchronous to some
clock it is not necessarily synchronous to the clock used for that
interface. So always generate a local reset signal to avoid problems that
could result from this.
While we are at it also update the code to only generate a local reset if
the interface is asynchronous to the register map, otherwise use the
register map reset.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-22 13:22:23 +02:00
5edcc753ec
axi_dmac: Ignore timing on more debug signals
...
Ignore the timing path from the current DMA address to the register map,
this is just a debug signal at the moment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-22 13:22:23 +02:00
ae808ba942
axi_dmac: Fix block ram constraint
...
If the internal FIFO is larger than one block ram there will be multiple
BRAMs called ram_reg[0], ram_reg[1]. Modify the BRAM constraint rule so that
it matches these as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-21 19:56:42 +02:00
a100ecd308
util_dacfifo: Update BRAM DAC Fifo
...
The fifo will be placed between the DMAC and the Upack module, all the interfaces were updated.
2015-04-21 15:45:56 +03:00
988bf60747
axi_ad9361: Add ASYNC_REG properties to CDC regs and add missing -datapath_only
...
Set the ASYNC_REG property on the bit synchronizer CDC control regs. This
hint to Vivado that the registers are used for CDC purposes.
Also use -datapath_only for the set_max_delay constraints on the CDC data
path to remove the hold time requirement.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-21 10:15:02 +02:00
996d0fe8a4
axi_hdmi_tx: Only mark HDMI clocks asynchronous to each other
...
Currently the axi_hdmi_tx core constraints marks all its clocks asynchronous
to all other clocks in the system. This is a bit unfortunate as these
constraints are not restricted to the axi_hdmi_tx, but affect all cores in
the system, some of which might actually have timing constraints on CDC
paths.
The proper way to fix this is to add constraints for the axi_hdmi_tx core
CDC paths. For now only mark the interface clock asynchronous to the HDMI
clock, as this is easy to do and an improvement over the current situation,
as other cores are no longer affected.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 20:18:51 +02:00
e3b834ea02
axi_ad9361: Add CDC constraints
...
Add proper constraints for all the CDC synchronizer paths to the axi_ad9361
core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 20:12:06 +02:00
0dc3bb8905
axi_dmac: Fix src_reponse_fifo control signals
...
The src_response_fifo has been removed from the design, but we still need to
assert the ready and empty control signals for things to work properly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 19:51:37 +02:00
42a9da0659
axi_dmac: Only apply CDC constraints if clocks are asynchronous
...
We really only want to apply the CDC constraints if the clocks are actually
asynchronous. Unfortunately we can't use if ... inside a xdc script. But we
can use expr which has support for a ? b : c if-like expression. We can use
that to create helper variables that contains valid clock when the clock
domains are asynchronous or {} if they are not. Passing {} as
set_false_path/set_max_delay as either the source or destination will cause
it to abort and no constraints will be added.
Also add -quiet parameters to avoid generating warning if the constraints
could not be added.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 17:20:25 +02:00
9c249d25ab
axi_dmac: Make internal resets active high
...
All the FPGA internal control signals are active high, using a active low
reset inserts a extra invert LUT. By using a active high reset we can avoid
that.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 17:20:25 +02:00
dc2b37bd0c
Makefile: Added top level Makefile. Modified behavior of clean and clean-all
...
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
fd2f5836f0
axi_dmac: Fixed type in the altera hardware file
2015-04-17 14:59:47 +03:00
dfc22fc7de
axi_i2s_adi: Overhaul CDC
...
* Generate a separate synchronous reset for the data clock domain.
* Add missing stage to toggle synchronizers.
* Give a common prefix to CDC elements and add the proper constraints to the
XDC file
* Remove some unnecessary resets
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:28 +02:00
8289262807
axi_spdif_tx: CDC overhaul
...
Use common prefix for CDC elements and add the proper constraints to the XDC
file. And add a missing stage to the toggle synchronizers.
Also drop a some unnecessary resets.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:28 +02:00
9183f2287a
axi_spdif_tx: Use adi_ip_constraints
...
Use adi_ip_constraints to add the constraints file instead of open-coding
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:28 +02:00
bfd84edc46
adi_ip.tcl: adi_ip_constraints: Add support for VHDL projects
...
Match both xilinx_verilogsynthesis and xilinx_vhdlsynthesis when getting the
file group.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:28 +02:00
7c97e192f2
dma_fifo: Simplify FIFO WE condition
...
The only time we must not write to the FIFO is when it is full as this will
overwrite the first sample. Under all other conditions it is ok to write
data. If that data is invalid it will be overwritten when valid arrives.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:22 +02:00
374f82e7de
makefiles: The clean command for library won't remove the xml files, except for component.xml.
...
Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
34aa0cfda2
Partially revert "axi_dmac: Set proper constraints"
...
This partially reverts commit f51c941c2d
2015-04-16 10:01:19 +02:00
f13666cd81
ad9361: axi_dmac_constr: Fix typo
2015-04-16 10:01:19 +02:00
f51c941c2d
axi_dmac: Set proper constraints
...
Instead of just marking all clock domains as asynchronous set the
appropriate constraints for each CDC path.
For single-bit synchronizers use set_false_path to not constraint the path
at at all.
For multi-bit synchronizers as used for gray counters use set_max_delay with
the source clock period domain to make sure that the signal skew will not
exceed one clock period. Otherwise one bit might overtake another and the
synchronizer no longer works correctly.
For multi-bit synchronizers implemented with hold registers use
set_max_delay with the target clock period to make sure that the skew does
not get to large, otherwise we might violate setup and hold time.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:26 +02:00
b14721b8ae
library: Use common prefix for CDC signal names
...
Use a common naming scheme for CDC signals to make it easier to create
constraints for them.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:22 +02:00
c9206433b5
adi_ip.tcl: Allow to specify processing order for adi_ip_constraints
...
In order to be able to use get_clocks in a constraint file the constraint
file needs to run after the constraint file that creates the clock. Allow to
specify the processing order when adding a constraint file to a core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:15 +02:00
24df683a2a
axi_dmac: Disable src_response_fifo for now
...
The result of the src_response_fifo is currently not used so disable it for
now.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:12 +02:00
4062aa2860
util_axis_fifo: Fix reset signal
...
Some of the synchronizers were using the wrong reset signal, fix this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:11 +02:00
762fa3290b
util_axis_fifo: Add room and level outputs
...
Add a room output on the input side that reports how many free entries the
FIFO has and a level output on the output side that reports how many valid
entries are in the FIFO.
Note that the level output is only accurate if the output of the FIFO is not
registered, otherwise it might be off by one.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:09 +02:00
ae4e7a0c37
util_axis_fifo: Add option to disable registered output
...
Add a option to specify whether the FIFO should have a registered output
stage or not. This is useful if the user wants to implement that stage
itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:08 +02:00
f6594e276e
Bring back AXIS FIFO as a separate module
...
Bring back the AXIS FIFO as a separate module instead of embedding it into
the DMAC module. This makes it possible to use it in other modules outside
of the DMAC.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:06 +02:00
8fc4b0630e
util_axis_resize: Fix typo
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:04 +02:00
cb98e3e151
adcfifo: unused process
2015-04-13 13:31:50 -04:00
95e41e50a6
axi_dmac: Make all clocks asynchronous
2015-04-11 12:04:55 +03:00
7d22399860
util_axis_resize: Fixed makefile
2015-04-09 18:06:56 +03:00
e9bd4b3512
axi_dmac: Updated altera core dependency, changed fifo files location
2015-04-09 17:58:21 +03:00
780455d68c
Makefile: Updated makefiles. Added makefiles for altera
2015-04-09 17:57:06 +03:00
b7d8e38c94
util_dacfifo: General update
...
+ Clean out the code, delete unnecessary flops
+ Add support for channel count (C_CH_CNT)
+ FIFO write (data from DMAC/upack) : valid just when xfer_req is asserted, address is free running, new xfer_req resets the address
+ FIFO read (data to DAC) : free running, reads to max address
2015-04-09 11:43:37 +03:00
668b8bda62
util_axis_resize: Add support for specifying the endianness
...
Add support for specifying whether the lsb of the larger bus are mapped to
the first or the last beat on the smaller bus.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
f1eb1c6064
util_axis_resize: Add support for non power-of-two ratios
...
Update the axi_repack core so it can handle non power-of-two ratios between
the input and output stream width. The ratio still needs to be a integer
though.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
b6458f9aab
axi_dmac: Move axi_repack block to its own module
...
Move the axi_repack block to its own module. This allows it to use it
outside of the DMA controller.
Also rename it to util_axis_resize to better reflect its function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
8a47d0f94b
adi_ip: Add helper function to add dependency to a IP core
...
Add a helper function that allows to add dependencies to IP cores to the
current IP core, this makes it possible to use a module from the other IP
without having to add the file itself to the current core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:52:41 +02:00
88abf98bd6
adi_env.tcl: Make default ad_hdl_dir path detection more robust
...
Instead of using a path relative to the current working directory use a path
relative to the location of the adi_env.tcl script.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 14:43:56 +02:00
bdaad46704
axi_dmac: Remove up_write signal
...
up_write is just an alias for up_wreq these days. Just always use the later
and remove the former.
2015-04-08 14:43:56 +02:00
98609527e3
axi_i2s: Add I2S interface definition
...
Using interface definitions makes it possible to group pins of a peripheral
into a interface pins. This allows us to use connect_bd_intf_net to connect
all pins of the interface instead of having to manually call connect_bd_net
for each for the pins.
Using interface pins also unclutters the connections in the Vivado block
design view a bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
86e6f67d4b
util_i2c_mixer: Add I2C interface
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
fa696adc98
util_dac_unpack: Add fifo_wr interface
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
978f41cbe8
util_adc_pack: Add fifo_wr interface
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
6ba0667939
axi_dmac: Add fifo_wr/fifo_rd interfaces
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
c82b186610
Add interface definitions for the fifo_rd and fifo_wr interfaces
...
Using interface definitions makes it possible to group pins of a peripheral
into a interface pins. This allows us to use connect_bd_intf_net to connect
all pins of the interface instead of having to manually call connect_bd_net
for each for the pins.
Using interface pins also unclutters the connections in the Vivado block
design view a bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
11cc18be79
adi_ip.tcl: Initialize ip_repo_paths
...
Initialize ip_repo_paths so that when building a peripheral we have access to the interface definitions stored in the repository.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
d17cd22ef1
adi_ip.tcl: Allow to directly specify the vlnv string for adi_add_bus()
...
Modify the adi_add_bus() function to take the full vlnv strings instead of just the bus type.
This makes the function more flexible and e.g. allows to handle buses from other vendors.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
0d0c15df98
axi_adcfifo: fix file names
2015-04-07 16:40:52 -04:00
5f8e9a74ea
makefile: updated
2015-04-07 16:32:01 -04:00
922ea7fb34
util_sync_reset: removed
2015-04-07 16:28:05 -04:00
6d0a2bf64c
axi_adcfifo: added
2015-04-07 16:21:39 -04:00
e73e563a02
util_adcfifo_axi: removed
2015-04-07 16:16:51 -04:00
712becd57f
adcfifo: axi version
2015-04-07 16:16:17 -04:00
4f7f109056
util_adcfifo: added
2015-04-07 16:08:38 -04:00
dfaa6f6571
fifo2s: removed
2015-04-07 16:01:36 -04:00
3c316efbc5
fifo2dac: removed
2015-04-07 16:01:21 -04:00
69cadd46ed
adcfifo_axi: added
2015-04-07 16:00:47 -04:00
056d6bbf40
dacfifo: added
2015-04-07 15:55:29 -04:00
99c124e708
fifo2f: removed
2015-04-07 15:53:22 -04:00
9098e3ebca
fifo: removed
2015-04-07 15:52:31 -04:00
86a70b3054
adcfifo: added
2015-04-07 15:43:02 -04:00
7224ca1f0c
dma: moved
2015-04-07 15:35:47 -04:00
9fa3131858
axi_fifo2dac: Initial commit
...
BRAM fifo for high speed DACs
2015-04-07 17:46:36 +03:00
de2c3764d6
util_upack: Updated IP, added upack_valid and dma_xfer_in/dac_xfer_out ports.
2015-04-07 16:55:25 +03:00
8af60576cd
dma: constraints
2015-04-06 13:38:31 -04:00
f79a152958
Makefiles: updated all makefiles adding clean functionality
2015-04-03 11:57:54 +03:00
ba2e635918
makefile: added
2015-04-01 16:28:20 -04:00
2f41aebaa9
makefile: added
2015-04-01 16:28:19 -04:00
a5f937a96d
makefile: added
2015-04-01 16:28:18 -04:00
8b09fedae9
makefile: added
2015-04-01 16:28:16 -04:00
64601272da
makefile: added
2015-04-01 16:28:15 -04:00
e0c7ad802a
makefile: added
2015-04-01 16:28:14 -04:00
b0db485e0d
makefile: added
2015-04-01 16:28:13 -04:00
a10c7a4245
makefile: added
2015-04-01 16:28:11 -04:00
afb7115b2f
makefile: added
2015-04-01 16:28:10 -04:00
90298816e4
makefile: added
2015-04-01 16:28:09 -04:00
96c81013ac
makefile: added
2015-04-01 16:28:08 -04:00
20280fecbe
makefile: added
2015-04-01 16:28:06 -04:00
8ec8c966b1
makefile: added
2015-04-01 16:28:05 -04:00
63efcbf4ca
makefile: added
2015-04-01 16:28:04 -04:00
1d3129a600
makefile: added
2015-04-01 16:28:03 -04:00
00411a53da
makefile: added
2015-04-01 16:28:01 -04:00
15c25ac45b
makefile: added
2015-04-01 16:28:00 -04:00
a63d4ae65c
makefile: added
2015-04-01 16:27:59 -04:00
4222b35292
makefile: added
2015-04-01 16:27:58 -04:00
9ced8643c6
makefile: added
2015-04-01 16:27:56 -04:00
109a38e0e8
makefile: added
2015-04-01 16:27:55 -04:00
871460016d
makefile: added
2015-04-01 16:27:54 -04:00
c0a4c6e046
makefile: added
2015-04-01 16:27:52 -04:00
5a5ffb7745
makefile: added
2015-04-01 16:27:51 -04:00
54ee0a0273
makefile: added
2015-04-01 16:27:50 -04:00
3dbbb4e5bb
makefile: added
2015-04-01 16:27:49 -04:00
566e8d7fd3
makefile: added
2015-04-01 16:27:47 -04:00
500f71af2f
makefile: added
2015-04-01 16:27:46 -04:00
4e7538fc8b
makefile: added
2015-04-01 16:27:45 -04:00
13a40af558
makefile: added
2015-04-01 16:27:44 -04:00
36b629dab1
makefile: added
2015-04-01 16:27:42 -04:00
856220e9e9
makefile: added
2015-04-01 16:27:41 -04:00
43f5025ecd
makefile: added
2015-04-01 16:27:40 -04:00
5b18d12c23
makefile: added
2015-04-01 16:27:39 -04:00
f20ab424f7
makefile: added
2015-04-01 16:27:37 -04:00
4ab17615ce
makefile: added
2015-04-01 16:27:36 -04:00
234d4ae7f3
makefile: added
2015-04-01 16:27:35 -04:00
55406b7a61
makefile: added
2015-04-01 16:27:34 -04:00
6cff03390c
makefile: added
2015-04-01 16:27:32 -04:00
a97fc603f8
makefile: added
2015-04-01 16:27:31 -04:00
35205c43a1
makefile: added
2015-04-01 16:27:30 -04:00
1b5737968a
makefile: added
2015-04-01 16:27:29 -04:00
6ac43fe516
makefile: added
2015-04-01 16:27:27 -04:00
c2e626d0b6
axi_hdmi_tx: es split
2015-04-01 15:08:24 -04:00
3bca324c33
hdmi_rx: 64bit + es split
2015-04-01 14:25:55 -04:00
56165b89f7
hdmi_rx: 64bit + es split
2015-04-01 14:25:49 -04:00
01d0b495ec
hdmi_rx: 64bit + es split
2015-04-01 14:25:45 -04:00
d4763fe356
hdmi_rx: 64bit + es split
2015-04-01 14:25:41 -04:00
11d94b736a
util_gmii_to_rgmii: Added to dev branch
2015-04-01 17:22:49 +03:00
ae26c7817e
Remove util_sync_reset
...
The util_sync_reset peripheral hasn't been used in a while and will not be
used in new projects. So remove it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-01 14:46:41 +02:00
fd7a423f74
axi_dmac: Reset data stream resize blocks when disabled
...
When the DMA controller gets disabled in the middle of a transfer it is
possible that the resize block contains a partial sample. Starting the next
transfer the partial sample will appear the begining of the new stream and
also cause a channel shift.
To avoid this make sure to reset and flush the resize blocks when the DMA
controller is disabled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-01 14:18:34 +02:00
2d7bae2ba6
axi_mc_controller: Added delay module
2015-04-01 12:22:20 +03:00
de12184038
axi_mc_speed: Updated for motor control revision 2
2015-04-01 11:43:22 +03:00
d5fa0071bd
axi_mc_current_monitor: Updated for motor control revision 2
2015-04-01 11:42:28 +03:00
6ee66df41e
axi_mc_controller: Updated for motor control revision 2
2015-04-01 11:41:33 +03:00
4b1d9fc86b
axi_dmac: Modified in order to avoid vivado crash
2015-04-01 11:39:25 +03:00
e116822059
imageon_zc706: Updates and fixes
...
+ sync the sof to the dma_de signal
+ hdmi_rx_dma is connected to the HP1
+ fix syncronization signal in the CSC module
+ hdmi_rx_clk is asynchronous
2015-03-27 18:57:32 +02:00
0e1a60e8b7
axi_dmac: Brought up the transfer request signal for the dest_fifo and dest_axi_stream interface.
2015-03-26 12:20:32 +02:00
6ee9b3a1e2
util_wfifo: Fixed reset
2015-03-25 15:34:21 +02:00
552d9b41f7
imageon: updates
2015-03-24 15:08:48 -04:00
b29e97f985
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
ffe410b2dd
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
09bb184505
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
f92011f72d
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
5d50d38c66
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
80c2a5a45d
axi_hdmi_rx: General clean up
2015-03-23 12:39:26 +02:00
8f5551718e
axi_fifo2s: false paths on up_xfer_toggle
2015-03-19 16:33:14 -04:00
7e15fd9e5b
util_upack: Fixed ip
2015-03-19 16:22:12 +02:00
bc04e5a4ce
axi_i2s_adi: Fixed pins directions
2015-03-12 17:22:52 +02:00
8dfcbdfd48
gt_channel/gt_common: simulation parameter warning fix
2015-03-06 12:36:07 -05:00
57e1f0e334
gt_channel/gt_common: simulation parameter warning fix
2015-03-06 12:36:03 -05:00
2d01955042
up_gt: change version dfe/lpm support
2015-03-05 09:47:16 -05:00
6995f63134
Add version check to adi_ip.tcl too.
2015-03-05 11:55:09 +02:00
1613f7fb41
cftl_cip: Add util_pmod_fmeter IP to library
...
Frequency meter IP for CN0332.
2015-02-23 17:20:12 +02:00
65bda6505e
axi_dmac: Correctly handle shutdown for the request splitter
...
We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
731e1c0996
axi_dmac: Use internal enable signal for the request generator
...
All components should use the internal 'do_enable' signal instead of the
external 'enable' signal. The former correctly incorporates the shutdown
sequence and does not get asserted again until the shutdown has been
completed. Using the external signal can cause problems when it is disabled
and enabled again in close proximity.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
582ea06918
axi_dmac: request_generator: Stop generating requests when disabled
...
Currently when the DMAC gets disabled the request_generator will still
generate all remaining burst requests for the currently active transfer.
While these requests will be ignored by the source and destination component
this can still take a fair amount of time for long transfers.
So just stop generating burst requests once the DMAC is being disabled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
aa594e15f3
axi_dmac: fifo_inf: Handle overflow and underflow correctly
...
Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:21 +01:00
6edcaa478a
adi_ip: updates for 2014.4
2015-02-19 11:11:39 -05:00
9cdec38532
gt- report device type
2015-02-17 11:43:57 -05:00
2442b6e929
gt- report device type
2015-02-17 11:43:50 -05:00
fccadcec31
jesd_gt: lpm/dfe programmable
2015-02-13 11:33:25 -05:00
de043ce130
gt_channel: lpm/dfe programmable
2015-02-13 11:33:04 -05:00
870ebdb562
up_gt: support lpm mode
2015-02-12 16:21:11 -05:00
1e7c9a3924
gt_es: support lpm mode - 2/2
2015-02-12 16:20:43 -05:00
0a8e6f62ef
gt_es: support lpm mode - 1/2
2015-02-12 15:15:18 -05:00
9e2e2ef44e
xfer-logic: stretch toggles to allow capture
2015-02-06 22:15:16 -05:00
e9231c8f36
xfer-logic: stretch toggles to allow capture
2015-02-06 22:15:14 -05:00
518d842af9
upack: initial commit
2015-02-06 15:15:33 -05:00
d02c21b426
util_pmod_adc: General update
...
Redesign the state machine, rename constant and variable names, add notes and description.
2015-02-04 14:49:16 +02:00
96899313d8
axi_dmac: Fix constraint
...
Change the constraint file extension to .xdc, no more need for the .tcl workaround.
2015-01-23 18:51:25 +02:00
b10ba49425
axi_dmac: Fix constraint related issue
...
Tcl command "if" is not supported by Vivado XDC, therefore the tool throw some critical warnings, and does not
apply the constraints, which can cause timing violations at case of some carriers.
The following solution is much more compact and is supported by the XDC, and more importantly prevents
unwanted critical errors and timing violations.
2015-01-23 18:44:17 +02:00
d5bd485624
axi_dmac: Fix eot issue under 2014.4
...
Vivado 2014.4 is too greedy, when it needs to optimize. See more about the issue here: https://ez.analog.com/thread/48214
The response_dest_resp is unused, so not save to concatenate with a valid signal like the eot.
2015-01-23 18:39:33 +02:00
659e0cca4e
cftl_cip: Initial check in.
...
Project cftl_cip supports the following Circuits from the Lab pmods:
+ EVAL-CN0350-PMDZ
+ EVAL-CN0335-PMDZ
+ EVAL-CN0336-PMDZ
+ EVAL-CN0337-PMDZ
Note: Additional testing needed!
2015-01-23 18:29:32 +02:00
5a1819ed6e
fifo2s: qualify last with valid
2015-01-15 15:42:10 -05:00
debbe31713
Merge remote-tracking branch 'origin/master' into dev
2015-01-09 11:12:56 -05:00
63633a0fa5
ad9739a: constraints
2015-01-08 10:25:45 -05:00
ed73a9d1cf
ad9739a: updated to ad9739a
2015-01-08 10:25:15 -05:00
14df46c193
library: Initial commit of axi_hdmi_rx ip core
...
Status unknown, NOT tested.
2015-01-08 16:58:56 +02:00
9f485f2f4e
common: Add register map module for HDMI receiver.
2015-01-08 12:24:47 +02:00
161e6cc70d
common: Add color space sampling and color space conversion modules
...
This two module are used by the HDMI receiver.
2015-01-08 12:24:46 +02:00
ad4b4f64d0
ad9739a: ad9122 copy
2015-01-07 15:36:02 -05:00
3a4d765a2b
up_clkgen: reading typo
2015-01-07 14:02:39 -05:00
b65bcab8d6
up_clkgen: reading typo
2015-01-07 13:58:43 -05:00
5f93c859b5
util_rfifo: renamed ports to make vivado happy
2015-01-06 16:16:42 -05:00
8056574bae
util_wfifo: renamed ports to make vivado happy
2015-01-06 16:16:25 -05:00
0291bb3bf7
util_rfifo: port name fixes & doc.
2015-01-06 16:15:51 -05:00
36b041ccc0
util_wfifo: port name fixes & doc.
2015-01-06 16:15:42 -05:00
ee0912eb6a
ad9361: make 2t2r external for mw
2015-01-05 10:54:23 -05:00
c3529f112f
up_gt: move status to up clock
2014-12-19 13:00:27 +02:00
f4774d6f98
fifo2s: false path typo on source signals
2014-12-19 13:00:13 +02:00
1d6ea64d04
up_gt: move status to up clock
2014-12-16 08:48:13 -05:00
16f64a75d6
fifo2s: false path typo on source signals
2014-12-15 13:00:13 -05:00
04c10abc2f
gth/gtx: share same cpll/qpll cpu settings
2014-12-11 11:18:48 -05:00
c4152627f0
plddr3: Sync adc_wcnt_int to adc_wr and fix adc_dwr pulse width
...
The adc_wcnt_int must be synchronized to adc_wr. The adc_dwr signal pulse width was to long,
it needs to be just one adc_clk cycle.
2014-12-09 13:59:19 +02:00
19732d89fb
plddr3: Fix the adc_dwr pulse width
...
The adc_dwr signal pulse width was to long, need to be just one adc_clk cycle.
2014-12-09 13:51:00 +02:00
6aad2fbbb2
axi_hdmi_tx: Fixed typo in altera related core
2014-12-09 10:19:03 +02:00
6f8c259961
axi_hdmi_tx: Fixed typo in altera related core
2014-12-09 09:56:14 +02:00
a70d27c094
axi_mc_speed: updated core to latest axi interface implementation
2014-12-05 11:53:11 +02:00
26f58914e2
axi_mc_current_monitor: updated core to latest axi interface implementation
2014-12-05 11:53:06 +02:00
7e8e1e4fd0
axi_mc_controller: updated core to latest axi interface implementation
2014-12-05 11:52:59 +02:00
ea1a50c985
axi_mc_speed: updated core to latest axi interface implementation
2014-12-05 11:46:20 +02:00
0d2888a5a6
axi_mc_current_monitor: updated core to latest axi interface implementation
2014-12-05 11:45:37 +02:00
21591dc485
axi_mc_controller: updated core to latest axi interface implementation
2014-12-05 11:43:59 +02:00
6197563506
up_axi: Fix up_raddr/up_waddr port width
...
Make sure that the port declaration width matches with the reg declaration
later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:45:45 +01:00
8cc9adfc49
up_axi: Fix up_raddr/up_waddr port width
...
Make sure that the port declaration width matches with the reg declaration
later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:22:28 +01:00
afddc45ba4
library/ccat: initial commit
2014-11-25 12:59:51 -05:00
196e8b119c
library/bsplit: initial commit
2014-11-25 12:59:50 -05:00
403f8c0631
util_cpack: ipi doesn't like local params
2014-11-21 15:32:13 -05:00
3b500bafcc
util_cpack: add port controls on ipi
2014-11-21 15:32:12 -05:00
5ca2944b70
library/util_cpack: initial checkin
2014-11-21 15:32:10 -05:00
42874bfe81
prcfg_library: Major update
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Get rid of the QPSK symbol wrapper for now. The DMA data path is using the 2 LSB bits.
2014-11-18 10:05:52 +02:00
a4724f8396
es: added kcu105 gth
2014-11-17 09:55:12 -05:00
b1c91fac92
es: added kcu105 gth
2014-11-17 09:55:10 -05:00
fd305f2eff
es: added kcu105 gth
2014-11-17 09:55:09 -05:00
6dd1226696
axi_ad9643: Fixed constraint file
2014-11-17 12:12:09 +02:00
8831d9dbd7
axi_ad9122: fixed constraint file
2014-11-17 12:11:20 +02:00
2744d0cb37
util_wfifo: Update to implement flip flops
2014-11-17 12:10:21 +02:00
41ffc66c26
fifo2s: removed m interface
2014-11-13 15:00:03 -05:00
8761db438e
axi_fifo2f: common interface with fifo2s
2014-11-12 15:15:32 -05:00
925e966eb6
axi_fifo2s: fifo full replaced with ready
2014-11-12 14:43:47 -05:00
5fc4f1b000
axi_fifo2s: buswidth fix
2014-11-12 14:43:46 -05:00
d204a7c2b7
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:44 -05:00
e7cec7171e
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:43 -05:00
4381f20a6a
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:42 -05:00
9f2dbad539
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:41 -05:00
e683b5868e
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:40 -05:00
81b4cd532d
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:38 -05:00
888ab888d2
axi_fifo2s: include bus width/clock transfer
2014-11-12 14:43:37 -05:00
f8e7796592
axi_jesd_gt: Fix lane number parameters
2014-11-12 17:43:32 +02:00
bf62665c56
prcfg_qpsk: Add Simulink model
...
Matlab version used: R2014a, HDL Coder 3.3
2014-11-12 15:44:38 +02:00
64ec633438
gt: asymmetric no of lanes
2014-11-11 08:54:24 -05:00
cb15567a56
ad6676: added
2014-11-10 13:36:07 -05:00
c6df568a00
Revert "ad_interrupts: Initial check in."
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This reverts commit b254380338
2014-11-06 12:16:52 +02:00
b11d80ed98
ad_rst: changed to dual stage
2014-11-05 16:48:02 -05:00
74ec396b27
ad_rst: ultrascale -dual stage
2014-11-05 16:47:41 -05:00
d69ccebbde
ad9234: full 16bit samples
2014-11-05 11:59:08 -05:00
403fe1b373
wfifo: read only if ready is asserted
2014-10-31 13:05:17 -04:00
38652b1c3e
axi_ad9643: Added constraint file
2014-10-31 17:57:47 +02:00
3e9ce71d21
axi_ad9122: Added constraint file
2014-10-31 17:56:56 +02:00
d596d71285
prcfg_qpsk: Swap the I/Q pair nets between the filter and the demodulator.
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This fix the wrong symbol mapping issue.
2014-10-31 12:14:52 +02:00
eb520b1f75
prcfg_qpsk: Major update
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Add a symbol wrapper to the logic. Wraps the 32 bit data to 2 bit symbols.
2014-10-31 12:10:59 +02:00
ea194755e1
prcfg: Upgrade the QPSK logic
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Regenerate the qpsk logic, with the new HDL coder, and modify the design to support the new files.
2014-10-31 11:59:29 +02:00
9818bcb601
axi_fifo2f: internal memory low overhead
2014-10-30 11:12:10 -04:00
17cb1d9585
common/mem: asymmetric version
2014-10-30 11:12:09 -04:00
6470ea91ad
axi_fifo2f: fake version
2014-10-30 11:12:08 -04:00
f9628262aa
axi_dmac: Add xfer_req signal to the streamin AXI source interface
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-29 18:15:54 +01:00
fbce64411e
axi_ad9671: added synchronization interface to altera core
2014-10-29 18:20:26 +02:00
36c7034bd6
ad7175: Fix dma issues
2014-10-28 16:00:06 +02:00
9c8fe5f09c
ad7175: Removed unused files
2014-10-28 14:30:41 +02:00
9e1d1c1b49
ad7175: Updated the AD7175 IP and project
2014-10-28 14:28:38 +02:00
b254380338
ad_interrupts: Initial check in.
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Initial check in of the interrupt concatenation block.
2014-10-27 19:34:34 +02:00
e086f5eb9f
axi_ad9361: Updated core with the new up_adc_common register set
2014-10-27 19:26:40 +02:00
7e52cf9568
up_axi: timeout generating multiple/repeated acks
2014-10-23 13:51:33 -04:00
3dbfa8cda6
ad9434_fmc: Fix PN monitor and device interrupt
2014-10-23 11:29:14 +03:00
b9ca616150
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-23 06:11:52 +03:00
da8454ae4c
axi_ad7175: Added the AD7175 IP
2014-10-23 06:11:41 +03:00
6f723ef9e5
axi_jesd_gt: lane mux on char qualifiers
2014-10-22 15:29:25 -04:00
fe92b8b210
axi_ad9671: Updated synchronization mechanism to have a software defined starting code
2014-10-22 13:10:28 +03:00
121a416916
axi_dmac: Fixed constraints for axi_dmac core
2014-10-22 13:07:55 +03:00
1d26639d73
common: Added synchronization mechanism to the up_adc_common module
2014-10-22 10:05:55 +03:00
4b19646ed9
ad9434_fmc: Fix samples order.
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Four consecutive samples were reversed.
2014-10-21 16:34:28 +03:00
46d1710539
axi_ad9625: added constraints
2014-10-17 13:57:30 -04:00
37b608f397
axi_ad9144: added constraints
2014-10-17 13:57:09 -04:00
df3915e2b0
ad9625: constraints added
2014-10-17 13:41:56 -04:00
819a3d0802
util_adc_pack: removed latches
2014-10-17 15:40:16 +03:00
9d43a08865
gt: constraint modifications
2014-10-15 14:51:01 -04:00
86724f7fc7
gt: tx lane interleaving
2014-10-15 14:51:00 -04:00
206b96d55a
ip: constraint changes
2014-10-15 14:50:58 -04:00
f0b25c39a3
wfifo: added axi stream support
2014-10-15 14:50:56 -04:00
51a15a28b7
axi_fifo2s: added constraints
2014-10-15 14:50:53 -04:00
8934a66013
usdrx1: Update project so that the AD9671 cores can be synchronized
2014-10-13 17:06:40 +03:00
3d5ef9a8ed
util_dac_unpack: Fix unpack order with 1 channel
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Due to the delay between the dac_valid and the fifo_valid signal we need to
have two counters. One counter which counts the number of incoming
dac_valid signals and generates the dma_rd signal and one counter for the
offset which gets set to 0 when fifo_valid is set.
This fixes issues with the unpack order when only one channel is active.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:14 +03:00
dd70320b00
axi_spdif: Add missing signals to the regmap read sensitifity list
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:09 +03:00
e7af6219dd
axi_spdif: Don't use non-static expressions in port assignments
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Fixes a warning from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:05 +03:00
ab5eee42e4
axi_spdif: Set unused signals to 0
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Fixes warnings about undriven signals from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:26:00 +03:00
0b587e6fb1
axi_i2s: Add missing signals to the regmap read process sensitivity list
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:56 +03:00
cf2bbf66b7
axi_i2s: Set unused signals to 0
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Fixes warnings from the tools about undriven signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:51 +03:00
22169c4a9c
axi_dmac: Add default driver values for optional input ports
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This silences warnings from the tools about undriven ports.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:46 +03:00
e7dbdff60c
axi_dmac: Hide fifo_wr_sync signal if C_SYNC_TRANSFER_START != 1
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The fifo_wr_sync signal is only used when C_SYNC_TRANSFER_START = 1, so hide it otherwise.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:41 +03:00
8557073b56
axi_dmac: Hide fifo_wr bus when source type is not the fifo interface
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:33 +03:00
3e6f553ce3
axi_dmac: Add clock signal spec for m_axis/s_axis bus
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This silences warnings from the tools about having no clock assigned to the bus.
Also fix the name of the TVALID signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:24 +03:00
c2ed80e8bb
axi_dmac: Drive unused signals to 0
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This silences a few warnings from the tools about undriven signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:49 +03:00
aee95ebe96
axi_dmac: Fix dummy AXI a{r,w}len fields width
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The dummy a{r,w}len fields should have the same width as the real a{w,r}len
fields in order to not break auto AXI bus version detection.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:43 +03:00
4f53a69f3c
util_dac_unpack: Hide unused signals
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Hide unused signals based on the number of selected channels. This silences
a few warnings from the tools about unconnected pins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:37 +03:00
77133fe60a
util_adc_pack: Hide unused signals
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Hide unused signals based on the number of selected channels. This silences
a few warnings from the tools about unconnected pins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:29 +03:00
3ab0f417b4
util_dac_unpack: Don't use localparam symbols in input/output signals
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When using a localparam for the width of a input/output signal the tools
won't be able to infer the size of the signal. This results in the signal
always being only 1 bit wide which causes the design to not work.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:19 +03:00
04e4458ee1
util_dac_unpack: Drive unused ports to 0
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Silences a few warnings about undriven ports from the tools.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:20:12 +03:00
61be003017
axi_i2s/axi_spdif: Create clock and reset interface for DMA bus
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This avoids some critical warnings from Vivado that the DMA bus does not has any associated clocks.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:41 +03:00
58cbe1813d
scripts/adi_ip: Add helper function to create bus clock and reset interface
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Add a helper function that can be used to register a clock and a reset interface for the clock and reset signals of a bus.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:31 +03:00
a31cb6c475
axi_i2s/axi_spdif: Remove manual creation of Streaming AXI bus
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It looks like Vivado is now able to infer these buses from the sources.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:11:06 +03:00
4bdb3cd262
axi_ad9671: altera axi4lite changes
2014-10-09 15:25:07 -04:00
6125bbecc3
axi_ad9671: altera axi4lite changes
2014-10-09 15:25:06 -04:00
2817ccdb22
up_axi: altera can not handle same clock assertion of arready and rvalid
2014-10-09 15:25:05 -04:00
5565cf8fad
axi_ad9467: Independent read/write update
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Independent read/write operation is supported on "up" interface
2014-10-08 11:23:44 +03:00
88a3b7f8fd
library: remove all constraints for now
2014-10-07 16:59:19 -04:00
2dfcb0c599
usdrx1: Initial commit for a5gt
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axi_ad9671: added start of frame information to the altera core.
2014-10-07 19:41:54 +03:00
a436153a48
axi_ad9434: Independent read/write update
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Independent read/write is supported on "up" interface.
2014-10-07 18:01:44 +03:00
9404e93126
ad9434_fmc: Fix PN monitor.
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No need to flop the incoming data.
2014-10-07 17:56:27 +03:00
66baf6ac3e
axi_ad9434: Deleted unused ip file
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ad_lvds_in.v is not used in this ip core.
2014-10-07 17:47:08 +03:00
bfa17844ff
ad_serdes_in: General update
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Added a parameter for option SDR / DDR mode, added a parameter for parallel data width.
Note: default IF_TYPE is SDR and default PARALLEL_WIDTH is 8
2014-10-07 17:42:27 +03:00
151781a2af
axi_ad9467: Fix PN sequence checker
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Make sure that the reference PN sequence is only incremented every two clock
cycles to make sure that it matches the rate of the ADC PN sequence.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-07 16:26:53 +03:00
59640f181b
ad9467: Fix LVDS delay interface.
2014-10-07 16:25:22 +03:00
c375b5b26e
daq3: vivado build
2014-10-06 10:34:02 -04:00
d47776a4a0
ad9152: 9144 copy
2014-10-06 10:34:01 -04:00
581892b22a
axi_ad9265: Updated project with new up independent read/write
2014-10-03 12:32:08 +03:00
de33722470
up/constr: independent read/write and local constraints
2014-10-02 14:35:59 -04:00
922bc6f03a
fmcadc3: 16bit - but ignored 4 lsb(s)
2014-09-29 15:26:30 -04:00
6a09a1ed19
ad9434: Fix the processor read interface
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Fix the processor read interface, preventing to have nets with multiple drivers. Made a few cosmetic changes in the code too.
2014-09-25 16:51:58 +03:00
ccb0b135ca
ad9434: Fix the adc to dma interface.
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All the device2dma interfaces needs to have a generic form : (data, enable, valid)/channel
2014-09-25 16:50:09 +03:00
d5f4991e26
ad9434: Merge the ad9434_if interface data outputs into one single bus
2014-09-25 16:45:12 +03:00
079ed0ffb3
ad_serdes_in: Update the serdes_in module
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Add additional IDELAY block before the ISERDES. Delet the IDDR blocks. Be aware, the ISERDES block are running in DDR mode. If the interface is SDR the maximum parallel data width is 4.
2014-09-25 16:40:29 +03:00
27ffff827a
common: Initial check in of ad_serdes_in.v
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A generic serdes module for input interface, support both 6 and 7 series.
2014-09-24 18:34:40 +03:00
683561b67d
AD9434: Initial check in of the library and project with ZC706
2014-09-24 18:27:17 +03:00
1d4bc47cea
ad9265: Initial commit
2014-09-23 22:51:42 -04:00
5af2474d51
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
2014-09-23 22:44:33 -04:00
1682d9da10
fmcadc3: initial updates
2014-09-22 11:27:17 -04:00
e528ee0b52
axi_ad9234: axi_ad9680 copy
2014-09-22 11:27:15 -04:00
de0edc2083
axi_dmac: src_fifo_inf: Clear pipeline when no transfers are active
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Clear the pipeline when no transfers are active to make sure that we do not
get residual data on the first sample for the next transfer.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-16 21:02:05 +02:00
c927e90ee1
axi_dmac/axi_fifo: Add missing file
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-15 21:04:57 +02:00
17a993032b
util_dac_unpack: Make number of channels and channel width configurable
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Always using 128bit for the input word unnecessarily increases the DMA
alignment requirements. This breaks existing software which assumes that the
DMA alignment requirement is 64bit.
So make it configurable whether we want 8 or 4 channels and while we are at
it also make the channel width configurable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:14:04 +02:00
61f21a17b3
fmcomms2:c5soc project upgraded with util_dac_unpack
2014-09-11 15:13:09 -04:00
3162540b03
axi_ad9361: Remove the Altera toplevel wrapper
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By setting the AXI controler interface type from axi4 to axi4lite we can use
the normal toplevel file with only a simple modification to add the awprot
and arprot signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:29:13 +02:00
36422f0454
axi_dmac: Remove Altera toplevel wrapper
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We can remove the Altera toplevel wrapper if we switch the axi4 control bus
to axi4lite and add the few missing signals that are required by the Altera
interconnect to both the control and the data buses.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:28:14 +02:00
b877cea2ed
up_axi: Add parameter to configure the internal address width
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Not all peripherals need 14 bit of address space.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:40 +02:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
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This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
6ad589475a
up_axi: Prevent read and write requests from racing against each other
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Make sure that if a read and a write request arrive on the very same clock
cycle to only accept one of them. The simple solution chosen here is to only
accept the write request when this happens and delay the acceptance of the
read request until the write request is finished.
This solution is not fair since a write request will always take precedence,
which in theory allows the write bus to starve the read bus. But in practice
we should never see that many write requests that we are unable to answer
the read request.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:04:05 +02:00
18a506b3ca
up_axi: Wait for the transaction to fully finish before releasing up_axi_access
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Wait for the master to accept the response for the current transaction
before we allow a new transaction to start.
This fixes problems in case the master is not ready to accept the response
when we make it available.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:03:52 +02:00
0da7b6eaa1
axi_dmac: axi_dmac_alt.v: Set default transfer length width to 24
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This is the same as the default value in axi_dmac.v
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:07:35 +02:00
a4b9b1254a
axi_ad9361/axi_dmac: Fix altrea AXI wrapper rid/wid handling
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We must make sure that the response ID is the same as the request ID when we
accepted the request. Otherwise we might respond with the wrong ID and the
system will lockup.
Also set rlast to 1 instead of 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
0966366514
motor_control: Updated the FOC IP
2014-09-08 15:52:18 +03:00
6e389b8c47
motor_control: Updated the FOC IP and the encoder connections to the IP
2014-09-06 15:58:03 +03:00
acde4f2c9a
axi_dmac: Added fix to work with motor_control
2014-09-03 12:10:34 +03:00
dfb94f7b68
motor_control: Modified foc_controller to be compatible with other cores
2014-09-03 12:09:37 +03:00
d08d0cd70b
motor_control: added the MW FOC IP and updated the design
2014-09-01 18:35:21 +03:00
a773cc4992
usdrx1: updated project
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ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
2014-09-01 15:18:39 +03:00
cf660c126d
util_adc_pack: Fixed problems when working in 4 channels mode
2014-08-29 13:51:40 +03:00
da913864c9
ad9671_fmc: updates to match recent core changes
2014-08-28 13:16:52 -04:00
272874f6ad
ad9652: pnmon fixes
2014-08-27 10:44:38 -04:00
31002c404c
util_adc_pack: Added parameters for configuring data width and number of channels
...
Valid values for the number of channels is 4 or 8
Valid values for datawidth is 16 or 32
2014-08-27 14:47:57 +03:00
58fa0776c9
axi_dmac: Added patch to fix issue on altera systems
2014-08-26 16:24:34 +03:00
5f21f54463
fmcjesdadc1: zc706 version
2014-08-25 14:28:57 -04:00
fe1eaefcff
fmcomms1: zc706
2014-08-22 09:08:55 -04:00
280260e54c
c5soc: dmac separated slave and master id widths
2014-08-22 09:08:54 -04:00
b481df0b5f
library: local constraints async groups
2014-08-14 15:09:51 -04:00
01963b01fc
jesd_gt: local constraints
2014-08-14 15:09:49 -04:00
9438e2a9e0
spdif: constraints file added
2014-08-14 15:09:48 -04:00
1396a215e5
library: local constraints
2014-08-14 15:09:47 -04:00
39bb7ca231
a5soc: fmcjesdadc1+hdmi version
2014-08-14 09:05:38 -04:00
2b15c7313e
ad_dcfilter: Fix filter loopback
2014-08-12 14:42:10 +03:00
a5e3a07375
dma: altera fix id assignments
2014-08-11 16:46:36 -04:00
9dfbf4a9a6
prcfg: Update the prcfg logic to the new ad9361 interface
2014-08-05 17:54:37 +03:00
08a12aaf23
library: register map updates on 9467, 9643 and 9671
2014-07-31 15:19:45 -04:00
dfd11cb809
ad9467: register map changes
2014-07-30 15:31:09 -04:00
c215eab696
ad9122: register map updates
2014-07-30 11:32:15 -04:00
b97bdcdc23
ad9122: register map updates
2014-07-30 11:32:13 -04:00
a2b728b91e
util_adc_pack: added extra registers to meet timing.
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Util_dac_unpack: fixed issue regarding changing from 1 channel to 2
2014-07-25 17:41:47 +03:00
26a019ae6e
util_adc_pack: Fixed issue regarding changing from 1 channel to 2
2014-07-25 10:20:49 +03:00
59759a8ab3
c5soc: working hdl version
2014-07-24 20:51:41 -04:00
6346017763
c5soc: changed to alt_lvds - 250M is too high for cyclone v
2014-07-24 20:51:40 -04:00
7000897031
fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
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The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
2014-07-24 19:57:22 +03:00
701dc96016
up_dac_channel: make iq cor coeff(s) tc
2014-07-24 10:10:24 -04:00
191f994e79
prcfg: Fixed the PRBS lock issue on BIST
2014-07-24 09:41:13 +03:00
db1c931736
ad9625_plddr: PL DDR3 fixes
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- Modified the axi slave interface handler
- Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
4da8100fe5
ad9625_plddr: Delete trailing whitespaces.
2014-07-23 19:31:07 +03:00
54b2cd74bf
motor_control: cores modified so they can compile with the new common files
2014-07-23 11:58:50 +03:00
c0e31aa6c2
daq2: latest hardware
2014-07-21 09:06:57 -04:00
2955b9db78
fifo2s: flush if no request, c5soc: 14.0
2014-07-15 16:25:33 -04:00
e7d5d79e42
daq2/kcu105: gth up and running - as it is commit
2014-07-10 10:56:37 -04:00
a9992f02b0
fifo2s: bug fixes- on 64mhz dma clock
2014-07-08 16:57:44 -04:00
b434fe6dd5
fmcomms5: register map changes
2014-07-08 16:57:43 -04:00
dc78ced443
prcfg_lib: Change the prcfg_top interface
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Use the device core's gpio_input and gpio_output registers to get/set
status and control of PR.
2014-07-08 12:28:25 +03:00
75e624ef15
prcfg_lib: Flop the status and mode nets
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Flop the status and mode nets in case of BIST and QPSK configurations.
2014-07-08 12:23:48 +03:00
39ac29bb01
AD9361: Altera, modified address width so that all registers are accessible
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Modified qsys project with the new address span
2014-07-08 10:41:51 +03:00
f3b20fd148
axi_ad9625: register map updates
2014-07-03 11:19:31 -04:00
1a78ac453e
Merge branch 'devel' of github.com:analogdevicesinc/hdl into devel
2014-07-02 15:39:42 -04:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
e4ce00f7fb
axi_ad9680: register map changes
2014-07-02 12:50:09 -04:00
7e5748374d
prcfg_lib: Fixed prbs generator for QPSK
2014-07-02 18:14:35 +03:00
8eb7a55797
prcfg_lib: Fixed the gpio status merge logic
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The previous logic did not passed implementation.
2014-07-02 18:09:48 +03:00
9089877c70
prcfg_lib: Fixed the sine tone generator for BIST
2014-07-02 18:00:43 +03:00
8a2b29cdbe
axi_damc: Add xfer_req to the FIFO source interface
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The xfer_req signal will be high if DMA core the is expecting data.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-07-02 16:05:16 +02:00
31abd07613
axi_ad9144: register map changes
2014-07-01 21:43:04 -04:00
60dd14bcdb
a5soc: removed jtag master control
2014-07-01 12:27:37 -04:00
b6052773b7
added adc/dac gpio registers
2014-06-27 14:45:58 -04:00
ba7955c531
fmcomms2: register map modifications
2014-06-26 10:09:03 -04:00
4afe6c24e9
Merge branch 'devel' of github.com:analogdevicesinc/hdl into devel
2014-06-25 15:26:21 -04:00
10a7804e14
ad9361: altera wrapper updates
2014-06-25 15:26:06 -04:00
4fdb3cfc4a
ad9250: register map updates
2014-06-25 15:23:57 -04:00
4f5d163fcc
Merge branch 'master' into devel
2014-06-25 13:07:12 -04:00
e38813fa9f
fifo- monitor status signals
2014-06-25 12:15:13 -04:00
4877df9bec
axi_fifo2s: make read dead slow
2014-06-25 09:20:57 -04:00
985ace533e
ad9361: remove unused modules
2014-06-24 14:26:40 -04:00
6b3312bbf9
library: register map changes and for mathworks
2014-06-24 14:24:22 -04:00
d4be46cc17
library: register map changes and for mathworks
2014-06-24 14:23:56 -04:00
e650253013
library: register map changes and for mathworks
2014-06-24 14:22:05 -04:00
89961c8dd7
prcfg_lib: Update the PR libraries
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+ Flop the control nets too inside the adc/dac module
+ Flop the gpio_out in prcfg_top
2014-06-13 20:35:35 +03:00
7efd6149f8
daq2: initial checkin
2014-06-12 15:54:25 -04:00
87bec07a22
ad9625: added multi-sync support
2014-06-12 15:45:34 -04:00
5189d200e7
axi_fifo2s: linux fix on interfaces
2014-06-12 15:30:13 -04:00
3e5990366e
axi_ad9625: initial release
2014-06-09 16:39:08 -04:00
bef6a9c32c
axi_ad9361: Split dma data into individual channels for both ADC and DAC
2014-06-07 17:15:31 +03:00
cf56a568c6
kcu105: GTH updates
2014-06-05 14:27:38 -04:00
ea22d29862
prcfg: Initial check in of PR modules
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Initial check in of the partial reconfiguraiton modules.
2014-06-05 14:58:14 +03:00
5b5bca400f
ad9361: added adc loopback
2014-05-27 14:47:59 -04:00
842cd98b61
ad9361: adc loopback option
2014-05-27 12:15:02 -04:00
56ddce1e8c
dmac: create fifo interface to avoid being treated as axi control stream
2014-05-27 10:25:14 -04:00
0cd43e34f5
dds: zero scale fix
2014-05-21 11:54:49 -04:00
916afd460f
axi_jesd_gt: synchronization support
2014-05-19 14:17:31 -04:00
3aed3ba71c
axi_ad9361: fmcomms5 changes
2014-05-19 12:41:12 -04:00
f73819f4d4
zc706: pl ddr3 initial checkin
2014-05-13 16:19:53 -04:00
a007add714
iqcorrection: missing input signals fix
2014-05-09 11:17:50 -04:00
f3f8374c75
ad9671: 2lane version
2014-05-08 18:33:26 -04:00
1d50489870
ad9361: ml605 updates
2014-05-05 11:03:57 -04:00
5f2fb45b24
library: ported hdmi tx to altera
2014-05-02 12:07:47 -04:00
a10043c4f4
kcu105: base complete with ethernet errors
2014-04-30 14:41:43 -04:00
ef60cce15e
kcu105: added
2014-04-30 14:41:40 -04:00
f55288ef5d
ad9671: altera - base changes
2014-04-28 21:31:18 -04:00
02e8b27626
initial checkin-9250 copy
2014-04-28 21:31:16 -04:00
01de117b5f
motor_control: Changed controller to PID controller. Some estetic changes
2014-04-28 17:57:51 +03:00
fa998a406b
dma: parameter fix
2014-04-24 15:50:16 -04:00
314ec3d343
altera-9250/dma: make id width generic
2014-04-24 14:54:19 -04:00
dfc2bba335
ad9671: updates to allow default adc setup routines
2014-04-23 16:39:28 -04:00
213e852e11
motor_control: Initial commit
2014-04-18 18:57:18 +03:00
503096de18
gt: change userready on drp clock
2014-04-17 16:09:55 -04:00
570ec26798
FMCOMMS2: Added sync option
2014-04-11 18:14:48 +03:00
99ef34936f
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-11 18:14:08 +03:00
c73390b6c9
axi_ad9361: Intermediary check in for altera porting
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This is work in progress. It will not work as it is
2014-04-11 17:40:34 +03:00
af07f8874f
wfifo/rfifo: asynchronous interface
2014-04-10 14:01:40 -04:00
96541f0a7f
usdrx1: zc706 updated for usdrx1
2014-04-10 11:05:13 -04:00
dc7b3e085c
axi_dmac: Fix issues with non 64-bit AXI masters
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Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:54:22 +02:00
36ef882da0
axi_dmac: data_mover: Improve timing
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We do not know which 'last' condition to use before hand, but we can pre-compute
the result for both conditions and then use them. This removes the comparison
from the already pretty long combinatorial path.
Also simplify a few expressions.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:06:44 +02:00
090d3aee04
axi_dmac: Change C_DMA_LENGTH_WIDTH default to 24
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
cb630e36a9
axi_dmac: src_fifo_inf: Simplify data path
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Improves timing a bit
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
f9ca4fb8be
axi_fifo: Slightly improve timing
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It is OK to overwrite invalid data with other invalid data.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
4c9647f289
axi_dmac: axi_register_slice: Provide default values for registers
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
fa5ba6c09d
axi_dmac: Make cyclic mode runtime configurable
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
7ca43f4920
axi_dmac: address_generator: Make 'len' registered
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Slightly improves the timing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
66e6c1cc21
axi_dmac: axi_register_slice: Remove reset "latch" from datapath
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Move the datapath updates out of the else branch of the reset condition.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
799d2384d8
up_xfer_cntrl: Remove extra semicolon
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
9d19145713
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-10 10:50:53 +03:00
5aac9d7288
FMCOMMS2 added sync option
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Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
e73952a694
ad9467 : initial checkin
2014-04-09 17:34:40 +03:00
8bebc5e3d4
ad9671: initial checkin
2014-04-07 13:01:10 -04:00
f8f2684b7e
up_gt: eyescan delay bug fix
2014-04-02 16:45:41 -04:00
e85153b5dd
altera hal version
2014-04-01 21:12:11 -04:00
80e5051894
axi_jesd_gt: initial checkin
2014-04-01 15:14:28 -04:00
2472d61daf
ad_gt_es: status asserted early for latency
2014-04-01 15:06:51 -04:00
0d678b89ed
altera a5gt fmcjesdadc1 setup
2014-04-01 11:46:37 -04:00
724bd70a06
altera additions and replacements
2014-04-01 11:18:10 -04:00
Rejeesh Kutty
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen
acozma
ATofan
U-ANALOG\ACostina
Istvan Csomortani