80dc3bf92f
daq2/a10gx: remove signal tap
2015-07-16 14:59:01 -04:00
1de74c0267
fmcadc4: Changed the SPI CS address similar to previous version
2015-07-16 18:22:05 +03:00
c949482574
fmcadc4: Set explicit PCORE_ID for AD9680
2015-07-16 18:21:49 +03:00
a7da779b94
Makefile: Updated Makefiles
2015-07-16 18:19:42 +03:00
4e99a2cb01
xcvr: remove signal tap
2015-07-16 08:09:56 -04:00
9f7fff2d2f
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
...
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 14:10:49 +03:00
7c142178dd
daq2/a10gx- axi_jesd_xcvr sysref name changes
2015-07-15 15:59:52 -04:00
ffd767deb2
daq2/a10gx- axi_jesd_xcvr sysref name changes
2015-07-15 15:59:51 -04:00
31584cf27e
ad9680- qsys needs interface signal name matching
2015-07-15 15:59:51 -04:00
60c344cea6
ad9144- qsys needs interface signal name matching
2015-07-15 15:59:51 -04:00
6c0ad6ede8
daq3: bsplit/ccat -- removed
2015-07-15 13:05:53 -04:00
29c6e90d38
util_bsplit: remove avalon streaming interface
2015-07-15 09:44:57 -04:00
af898de818
axi_jesd_xcvr: remove avalon streaming interface
2015-07-15 09:44:56 -04:00
ea57e49da7
axi_ad9250: remove avalon streaming interface
2015-07-15 09:44:54 -04:00
a454b73d27
fmcjesdadc1/a5gt: split xcvr cores
2015-07-15 09:44:53 -04:00
2d8fa2024b
fmcjesdadc1/a5gt: split xcvr cores
2015-07-15 09:44:52 -04:00
226e23ca1f
fmcjesdadc1- xcvr components
2015-07-15 09:44:51 -04:00
1dcbf5e5a2
fmcomms2/zc706: Fix GPIO connections
...
Fix GPIO connections for the FREQCVT board.
2015-07-15 15:12:01 +03:00
1f7745610e
daq2- ddr updates
2015-07-14 12:46:52 -04:00
a38339a3ec
fmcomms2/rfsom: Add GPIO control for the RF card
2015-07-14 13:12:54 +03:00
ba2029a6e8
fmcomms2/rfsom: Delete trailing whitespaces from system_constr.xdc
2015-07-14 13:12:53 +03:00
a2e7fb9491
daq2/a10gx: qsys signal tap version
2015-07-13 10:07:18 -04:00
6e3817d419
axi_jesd_xcvr: individual reset control
2015-07-13 10:04:34 -04:00
8d6c39d307
ad9680- remove avalon streaming
2015-07-13 10:03:38 -04:00
c69e36314c
ad9144- remove avalon streaming
2015-07-13 10:03:16 -04:00
825fddd034
transceiver split up outside qsys
2015-07-10 11:45:07 -04:00
8c0d74aa90
transceiver split up outside qsys
2015-07-10 11:44:42 -04:00
e40aac9ab6
transceiver split up outside qsys
2015-07-10 11:44:22 -04:00
9d95ddc620
reset and clock additions
2015-07-09 14:29:08 -04:00
897c31ebbf
imageon: moved spdif_rx to DMA3 to be compatible with both zc706 and zed
2015-07-09 10:58:54 +03:00
f1dd2435b4
signal tap removed
2015-07-08 15:47:31 -04:00
c9e73b023d
signal tap removed
2015-07-08 15:46:52 -04:00
f64df40a0a
signal tap removed
2015-07-08 15:47:50 -04:00
19bf05c740
signal tap removed
2015-07-08 15:47:48 -04:00
d6d263341e
signal tap needs another method
2015-07-08 15:47:47 -04:00
b25b2e3020
registers for signal tap
2015-07-08 15:47:45 -04:00
b4eb7465ed
library: Add missing Makefiles for axi_spdif_rx, util_jesd_align, util_jesd_xmit
2015-07-08 10:48:58 +03:00
bbf1c5b803
transceiver core added/gpio removed
2015-07-07 15:30:38 -04:00
23428ac48b
transceiver constraints for sysref
2015-07-07 15:25:36 -04:00
ea2bd71904
synchronize up signals separately
2015-07-07 12:51:13 -04:00
075b1e5424
daq2/a10gx: added axi_jesd_xcvr control
2015-07-07 10:22:36 -04:00
c1fcbeec8e
library/axi_jesd_xcvr: interface name matching
2015-07-07 10:21:53 -04:00
b106b8a8f4
library/axi_jesd_xcvr: updates
2015-07-06 13:51:55 -04:00
c67ca682a4
hw.tcl- added
2015-07-06 13:51:55 -04:00
1cfe6fe792
axi_jesd_xcvr: initial commit
2015-07-06 13:51:55 -04:00
3a5da47239
xcvr- initial checkin
2015-07-06 13:51:55 -04:00
46fa91d5be
Makefile: Update Make files
2015-07-03 18:08:57 +03:00
8c98399c37
imageon_ZC706: Add axi_spdif_rx core to the design
2015-07-03 17:48:29 +03:00
7376218e01
axi_spdif_rx: Initial commit
...
NOT tested.
2015-07-03 17:46:45 +03:00
27b786e92f
imageon_loopback: Use BUFIO for the HDMI clock buffer
...
Since we are just doing a loopback all the logic is contained within the
IO bank. By using a BUFIO instead of a BUFG we avoid having to route the
clock signal from the IO bank to the middle of the FPGA and back to the IO
bank. This reduces the skew between clock and the data signals and makes
sure that the we can use the same design over a range of different
resolutions without having to calibrate the delay.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
Rejeesh Kutty
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen