Rejeesh Kutty
|
7fdaee186c
|
upack/cpack- qsys ip
|
2016-05-18 13:24:13 -04:00 |
|
Rejeesh Kutty
|
a262eb7ab3
|
ad9361- output-rst - associated-rst issue?
|
2016-05-18 13:24:13 -04:00 |
|
Rejeesh Kutty
|
e15893444c
|
upack- fix interface names
|
2016-05-18 13:24:13 -04:00 |
|
Rejeesh Kutty
|
285cbc7225
|
xfifo- fix sdc/xdc names
|
2016-05-18 13:24:13 -04:00 |
|
Rejeesh Kutty
|
d7f0bd1b76
|
ad9361- add reset sink
|
2016-05-18 13:24:13 -04:00 |
|
Rejeesh Kutty
|
bb4ed42a93
|
ad9361- add missing wires
|
2016-05-18 13:24:13 -04:00 |
AndreiGrozav
|
42b0fabd40
|
axi_hdmi_tx_core: Fixed data path
|
2016-05-17 14:41:18 +03:00 |
|
Rejeesh Kutty
|
68329de738
|
ad9361- interface updates
|
2016-05-16 12:19:38 -04:00 |
|
Rejeesh Kutty
|
421c0519f4
|
util_rfifo- updates
|
2016-05-16 12:19:38 -04:00 |
|
Rejeesh Kutty
|
e05204a86d
|
util_cpack: interface updates
|
2016-05-16 12:19:38 -04:00 |
|
Rejeesh Kutty
|
6bc05fc844
|
ad_*_in: register post-iob
|
2016-05-16 12:19:38 -04:00 |
|
Rejeesh Kutty
|
cd7c9c99ed
|
ad_*_clk: altera-pll not supported by qsys flow
|
2016-05-16 12:19:38 -04:00 |
|
Rejeesh Kutty
|
4fbff45e27
|
util_wfifo- updates
|
2016-05-16 12:19:38 -04:00 |
|
Rejeesh Kutty
|
f515885fc4
|
util_wfifo: altera ip
|
2016-05-16 12:19:38 -04:00 |
|
Rejeesh Kutty
|
58a2a3259c
|
util_rfifo: updates
|
2016-05-16 12:19:38 -04:00 |
|
Rejeesh Kutty
|
82d43783f1
|
util_rfifo: altera ip
|
2016-05-16 12:19:38 -04:00 |
|
Rejeesh Kutty
|
31671bf9d5
|
util_rfifo: constraints
|
2016-05-16 12:19:38 -04:00 |
|
Rejeesh Kutty
|
aadb220a3f
|
zcu102- updates
|
2016-05-10 15:40:41 -04:00 |
|
Rejeesh Kutty
|
3871d3ce2b
|
ad9361-c5/a10 - updates
|
2016-05-09 13:54:08 -04:00 |
|
Rejeesh Kutty
|
9cd6e2da51
|
quartus-mess- altddio direct instantiation
|
2016-05-09 13:54:08 -04:00 |
|
AndreiGrozav
|
726ddb6e93
|
ad_lvds_clk: Fixed assignment mismatched
|
2016-05-09 10:32:18 +03:00 |
Istvan Csomortani
|
b0538a03a2
|
Make: Update
|
2016-05-06 16:44:24 +03:00 |
|
AndreiGrozav
|
b36c722ec9
|
up_hdmi_tx: Discard the standard default values
Restore the base functionality of the core. Changing the data format
will not set by default its standard maximum and minimum data clipping
ranges.
|
2016-05-05 13:41:46 +03:00 |
|
AndreiGrozav
|
68d83def01
|
axi_hdmi_tx_core: Fixed data path
|
2016-05-05 13:32:25 +03:00 |
|
AndreiGrozav
|
0d2dc2c62b
|
axi_hdmi_tx: Fixed data bus width
|
2016-05-05 13:26:59 +03:00 |
|
Rejeesh Kutty
|
bdfa383622
|
library/axi_ad9361: tdd false paths
|
2016-05-04 13:42:12 -04:00 |
|
Rejeesh Kutty
|
ef6c99ecab
|
library/axi_ad9361: hw component updates
|
2016-05-04 13:42:12 -04:00 |
|
Rejeesh Kutty
|
3b5e44e37d
|
library/axi_ad9361: mmcm rst for plls
|
2016-05-04 13:42:12 -04:00 |
|
Rejeesh Kutty
|
16a13b2023
|
library/axi_ad9361: add rst/locked to clock
|
2016-05-04 13:42:11 -04:00 |
|
Rejeesh Kutty
|
1aac44b0d9
|
library: ad_*clk- rst/locked
|
2016-05-04 13:42:11 -04:00 |
|
Rejeesh Kutty
|
d82ca5dc3c
|
library/common- altera variations
|
2016-05-04 13:42:11 -04:00 |
|
AndreiGrozav
|
b6b68e9ab7
|
axi_jesd_gt: Split the constraint file
-split axi_jesd_gt_constr.xdc file in rx, tx and common constraint files
-updated tcl script
|
2016-05-04 19:32:06 +03:00 |
|
Rejeesh Kutty
|
385ed31a45
|
make files update
|
2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
3f5e1e1203
|
ad9361- dev_if module name change
|
2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
89f5d2394e
|
altera- clock variations
|
2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
243d3e6e41
|
ad9361- a10soc sdc files
|
2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
aa2aa902bf
|
ad9361- a10soc updates
|
2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
f411d29e30
|
ad9361- a10soc changes
|
2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
3563c2212c
|
common/altera- removed dcfilt/mul
|
2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
0260280db1
|
common/altera- data path
|
2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
ed62101308
|
common/altera: primitives
|
2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
779d014750
|
ad9361-common alt/xil interface
|
2016-04-29 10:17:35 -04:00 |
|
Rejeesh Kutty
|
e9b199959a
|
library/adcfifo- constraints update
|
2016-04-20 15:57:25 -04:00 |
|
AndreiGrozav
|
679d471d75
|
Merge branch 'hdl_2016_r1' into dev
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
|
2016-04-19 18:05:50 +03:00 |
Adrian Costina
|
d7d8b2cf1c
|
axi_usb_fx3: Integrated actual GPIF II interface, with 2 address lines
|
2016-04-19 14:38:26 +03:00 |
|
Istvan Csomortani
|
e855ef38f4
|
axi_dacfifo: Initial commit
AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
|
2016-04-19 11:28:33 +03:00 |
|
Istvan Csomortani
|
42cd05ab19
|
ad_mem_asym: Add support for more ratios.
Supported ratios: 1:1/1:2/1:4/1:8/2:1/4:1/8:1
|
2016-04-19 11:18:30 +03:00 |
|
AndreiGrozav
|
6fe41ebb08
|
axi_hdmi_tx: Upgrade hdmi clipping process
-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
|
2016-04-12 22:01:07 +03:00 |
|
Istvan Csomortani
|
69d721526a
|
util_dacfifo: Add constraints file
|
2016-04-12 13:21:50 +03:00 |
|
Istvan Csomortani
|
255b0ebd40
|
util_dacfifo: Add dac_xfer_out control
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
|
2016-03-29 16:50:00 +03:00 |