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2765 Commits (7ed4955661271deec149901d2cc84272e2dfafb1)

Author SHA1 Message Date
Rejeesh Kutty 580808e146 axi_ad9361: added 2014-03-11 20:01:55 -04:00
Rejeesh Kutty a76d6c4686 library/axi_ad9122,axi_ad9643: added 2014-03-11 12:13:25 -04:00
Rejeesh Kutty e1f23e7d49 Merge branch 'master' of github.com:analogdevicesinc/hdl 2014-03-11 09:58:34 -04:00
Rejeesh Kutty 0817973cc0 library: removed xilinx dc filter and dds 2014-03-10 14:52:48 -04:00
Rejeesh Kutty f9dfd944c9 library/util_fifo: updates for read side 2014-03-10 14:48:14 -04:00
Rejeesh Kutty a6d747411e util_wfifo: ip cleanup 2014-03-10 11:21:20 -04:00
Rejeesh Kutty bb0431d3e8 library: dds and dcfilter changes, added fifo wrappers 2014-03-10 11:11:50 -04:00
Rejeesh Kutty d6256e9e29 library: dds and dcfilter changes, added fifo wrappers 2014-03-10 11:11:16 -04:00
Lars-Peter Clausen 8326022adc axi_dmac: address_generator: Fix disable race condition 
If the address generator is disabled the very same cycle as it tries to put a
new address on the bus, it will keep sending this address forever and the core
will lock up

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-07 18:40:49 +01:00
Lars-Peter Clausen 6da9c65a08 axi_dmac: Add support for zero latency transfer switching 
Right now there is always a period of one clock cycle where we can not transfer
any data when switching between two transfers. This patch modifies the data
mover to allow for zero latency. This fixes problems on the FMCOMMS1 platform

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-07 18:39:20 +01:00
Rejeesh Kutty 23a62a92b2 up_adc_common: dma bus width is 0x8 (constant) 2014-03-06 19:22:19 -05:00
Adrian Costina 831c19ea84 Added axi_dmac, axi_fifo and misc files in library 2014-03-06 18:16:02 +02:00
Rejeesh Kutty 63bd2b870a pointers to directories 2014-02-28 16:58:30 -05:00
Rejeesh Kutty ff5021b1a8 pointers to directories 2014-02-28 16:57:19 -05:00
Rejeesh Kutty f7c9368abc initial checkin 2014-02-28 14:26:22 -05:00