This commit adds a standalone TDD IP core based on the
existing up_tdd_cntrl module and the up_axi pcore <-> axi bridge.
Signed-off-by: David Winter <david.winter@analog.com>
If all channels are selected for read the values and ready signals from every
transceiver are combined. Each element merges his signals with the previous.
The first element of the chain must assume the previous channel is always ready.
This reverts commit 829e4155ca.
The first element of the read chain must assume there is no valid element
in front of it. For each element the ready signal of the transceiver should be
routed if the channel is selected either by channel number or broadcast.
When the current element is not selected it should forward the ready signal from
the previous element, however this is not the case for the first one.
Having a constant 1'b1 connected to the ready input of the first element
corrupts the first read of the first channel after a channel switch.
This change will break broadcast reads.
Adds a magic identification value of 0x54444443 at word address 0x3.
It is derived from the ASCII String "TDDC" interpreted as a big-endian
32-bit unsigned integer.
Signed-off-by: David Winter <david.winter@analog.com>
For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock
that is 2x of the CLKUSR2 (lane rate/66),
CLKUSR = 2 x CLKUSR2
CLKUSR = lane rate / 33
This can be driven from the GT reference clock or second out clock div2.
This commit also:
- fix eyescan scale on GTY
- remove irrelevant parameters
If R1 mode is first syncronized to the dac clock domain will prevent its
usage if the dac clock is missing. In such case the synchronization will not
propagate.
Depending on FPGA technology the physical layer uses different
deserialization factors and corresponding clock division factors to
divide the source synchronous interface clock. This must be
exposed to software so it can act on it while setting the DDS rate.
Xilinx CMOS clock ratio - 4
Xilinx LVDS clock ratio - 4
Intel CMOS clock ratio - 1
This module creates sync header alignment described in section 7.6.1 of
the JESD 204C specification.
The alignment relies on the bitslip capability of the connected
transceiver.
Create a common 'run_tb.sh' script to be called by every testbench.
Unify file and testbenches names.
Fix util_pack/cpack_tb.
Add parameters '-batch' and '-gui' for modelsim and xsim simulators (default is gui)
Add ascript for that generates output in xml format (used by CI tools).
get_cell on i_lmfc/cdc_sync_stage1_reg doesn't return anything because design was updated.
This generates a CRITICAL WARNING and since the constraint it not necessary anymore, it can be deleted.
If Tx source synchronous clock is not routed through clock capable pins
the interface and driving logic must run on the Rx interface clock.
This introduces a dependency, Rx interface must be bring up before the
Tx. In this mode a Tx only operation is not possible.
This is done through a synthesis parameter.
Expose this parameter to the software so it can query if the limitations
exists in the implementation.
If the REMOVE_NULL_BEAT_EN is set, in FIFO mode, all the beats with a
NULL TKEEP will be removed from the AXI stream.
This feature is used initially in data_offload, to create a continues and
cyclic TX data stream for DACs, when the IPs in the path have different data
widths.
Dual clock mode is introduced in link layer to support different
datapath widths on the transport layer than on physical layer.
- Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
- Device clock : Link clock * input data path width / output datapath width
Supports four clock configurations, single or dual clock mode with or
without external device clock.
The configuration interface reflects the dual clock domain.
Support multiple clock monitors in a block.
Before this change the clock monitor had to be named with a fix name
preventing multiple instances of the clock monitor.
Add parameter that describes interface to link layer, this must be
integer multiple of octets per frame.
Add parameter that describes interface to user/DMA, this must be
multiple of bytes so software can process the samples easier.
Make synthesis parameters accessible for the drivers.
Rework implementation to reflect the parameters of the actual core and
not of the AXI interfacing core.
To support deterministic latency with non-power of two octets per frame
(F=3,6) the interface width towards the transport layer must be resized
to match integer multiple of frames.
e.g Input datapath width = 4; Output datpath width = 6;
for F=3 one beat contains 2 frames
for F=6 one beat contains 1 frame
The width change is realized with a gearbox.
Due the interface width change the single clock domain core is split
in two clock domains.
- Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
- lane rate / 20 for input datapath width of 8 octets 8b10b
- lane rate / 66 for input datapath width of 8 octets 64b66b
- Device clock : Link clock * input data path width / output datapath width
Interface to transport layer and SYSREF handling is moved to device clock domain.
The configuration interface reflects the dual clock domain.
If Input and Output datapath width matches, the gearbox is no longer
required, a single clock can be connected to both clocks.
In order to keep resource utilization low and for better timing closure
allow disabling of the character replacement logic.
If the parameter is set the frame alignment monitoring is limited to links
where scrambling is on.
Add support to JESD204 RX and TX core for 8-byte 8b/10b link mode,
and frame alignment character replace/insert with or without scrambling.
Add support for xcelium simulator to jesd204/tb
Increased cores minor version.
There are boards (e.g. AD4630-24) which take the SCLK and echo back to
the FPGA through a level shifter - doing this removes the effect of
round-trip timing delays from the level shifter. This is commonly done
whenever isolators are used since they are very slow.
By setting the ECHO_SCLK parameter to 1, the IP will use the incoming
echoed SCLK clock to latch the SDI line(s). The sdi_data_valid is still
synchronous to the SPI clock, and it's generated after the last valid
SDI latch.
The designer's responsibility is to time the SDI shift registers in order to
respect the design requirements.
The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal
PRBS generators and checkers allowing the testing the multi-gigabit serial link
at the physical layer without the need of the link layer bringup.
alin724
David Winter
Laszlo Nagy
Alin-Tudor Sferle
AndreiGrozav
stefan.raus
Istvan Csomortani
Aaron Holtzman
Matt Blanton
sergiu arpadi