1fe0d5f8e0
data_offload: Fix timing violation
2021-09-22 12:18:33 +03:00
cdb9a0af2b
data_offload: Add sync to cyclic mode
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Signed-off-by: David Winter <david.winter@analog.com>
2021-09-21 09:06:03 +03:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
7423ecae14
data_offload: Improve external synchronization
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This commit adds a new synthesis option to the design, that controls
whether an internal clock domain crossing will be generated. Disabling
this option allows you to use a synchronization signal that is
synchronized to the write clock domain externally, and possibly shared
between multiple devices.
The default value retains the old behavior.
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-08 11:58:01 +03:00
235542cac9
data_offload: Fix support for > 4 GiB of storage
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This commit changes the transfer length register to work in increments of
64 bytes and without offset. The true transfer length can now be
determined by multiplying the value of the transfer_length register with
64.
A value of zero is interpreted as a request for all available storage.
Additionally, this commit fixes an off by one issue that was discovered
during testing of the RX path.
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
25038ccb4d
data_offload: Fix MEM_SIZE parameter width
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
58953ff40d
data_offload: Fix m_axis output stability issue
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
2b55c7453b
data_offload: Fix duplicated output samples
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
04f2d19d4b
data_offload: Fix data_offload getting stuck on oscillating m_saxis_ready
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
0af50d3f72
data_offload: Fix oneshot mode
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
66748510ea
data_offload: write_fsm: Always transition out of idle on high init_req
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
9faef440b2
data_offload: Bump hdl version
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
a89d0e6176
data_offload: Fix AXI register map
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
537a284115
data_offload: Fix readme images
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Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
6516b09a31
data_offload: Update README and generic block design
2021-08-06 11:55:24 +03:00
26518cdace
data_offload: Add block diagrams
2021-08-06 11:55:24 +03:00
9b1108ea87
data_offload: Flush the DMA if the transaction size is bigger than the storage
2021-08-06 11:55:24 +03:00
c82b0fb420
data_offload: Delete fifo_dst_rlast
2021-08-06 11:55:24 +03:00
0436a82f4e
data_offload: Fix alignment of write last beat and write full
2021-08-06 11:55:24 +03:00
378daf031c
data_offload: Improve timing in regmap
2021-08-06 11:55:24 +03:00
c27a0e4add
data_offload: Fix fifo_dst_ready generation
2021-08-06 11:55:24 +03:00
86b611c1f7
data_offload: Initial commit
2021-08-06 11:55:24 +03:00
Mihaita Nagy
David Winter
Adrian Costina
Istvan Csomortani