7e807d83b1
pzsdr1- cmos mode
2016-04-11 15:58:29 -04:00
bf6ef4e5f3
board- add disconnect
2016-04-11 15:33:00 -04:00
68bc647472
pzsdr1- ddr board delays update
2016-04-06 15:30:27 -04:00
7b01cd9eca
README.md: Update the README
2016-03-31 19:42:52 +03:00
1fab6ce477
daq2/common: Add util_dacfifo/dac_xfer_out control
2016-03-29 16:55:33 +03:00
255b0ebd40
util_dacfifo: Add dac_xfer_out control
...
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-03-29 16:50:00 +03:00
46eddd04be
library: port updates on mmcm
2016-03-22 12:50:59 -04:00
de4da6726b
axi_clkgen: port updates on mmcm
2016-03-22 12:50:59 -04:00
74408881c6
axi_ad9122: optional clock out control
2016-03-22 12:50:59 -04:00
65b2e51958
common/mmcm: add another clock
2016-03-22 12:50:59 -04:00
373481360b
util_dacfifo: Add a bypass option to the FIFO
2016-03-21 14:14:43 +02:00
896c734792
Revert "foobar"
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This reverts commit a3cb8cac45
2016-03-18 13:23:02 +02:00
a3cb8cac45
foobar
2016-03-18 11:51:13 +02:00
0905755db7
Update .gitignore file
2016-03-16 09:18:49 +02:00
697469ee28
daq1- updates
2016-03-15 12:39:38 -04:00
8ecf5edaf8
ad9122- pat modes
2016-03-14 11:14:29 -04:00
33b265a742
Makefile: Update Makefiles
2016-03-14 09:31:17 +02:00
561412e322
pzsdr-cmos swap
2016-03-11 11:25:58 -05:00
c7ee15d4f4
ccbrk_cmos: cmos mode
2016-03-11 11:25:58 -05:00
c566784ba9
ccbrk_cmos: ccbrk copy
2016-03-11 11:25:58 -05:00
287770a201
axi_dmac: Fix tlast generation on AXI stream master
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For the AXI stream interface we want to generate TLAST only at the end of
the transfer, rather than at the end of each burst.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-03-08 10:53:59 +01:00
b0f90bd0e8
daq1/cpld: Read interface fix
2016-03-04 20:28:24 +02:00
7e607957ee
daq1.cpld: Prevent the spi_counter to roll over.
2016-03-04 20:28:22 +02:00
262a42c676
daq1/cpld: Update CPLD_VERSION value
2016-03-04 20:28:20 +02:00
9439862301
daq1/cpld: Update CPLD
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Change to control line fpga_to_cpld to cpld_to_fpga, this is not a functional change.
2016-03-04 20:28:18 +02:00
583ef82fd0
ad9361- cmos mode
2016-03-04 10:39:48 -05:00
7a320a3d34
ad_lvds* - updates
2016-03-04 10:39:48 -05:00
3466f21f8e
pzsdr add cmos/lvds support
2016-03-04 10:39:48 -05:00
18f30c8dc8
pzsdr- cmos/lvds split
2016-03-04 10:39:48 -05:00
a2374f64bf
pzsdr- cmos/lvds split
2016-03-04 10:39:48 -05:00
7d2939be92
ad9361- cmos mode initial commit
2016-03-04 10:39:48 -05:00
977d9d0624
Merge branch 'hdl_2015_r2' into dev
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Conflicts:
projects/daq1/common/daq1_spi.v
2016-03-02 13:52:15 +02:00
40fb68dfd5
ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible
2016-03-02 13:39:37 +02:00
becc23a69b
daq2: Modified common spi module so that spi streaming is possible
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- stop incrementing spi_count after the instruction cycle
2016-03-01 17:25:58 +02:00
f7e490c2b3
hdlmake.pl updates
2016-02-26 13:46:11 -05:00
e012d0519b
Merge remote-tracking branch 'origin/hdl_2015_r2' into dev
2016-02-26 13:39:39 -05:00
f6e64e42b0
kcu105: add ethernet idelaycntrl
2016-02-26 13:19:49 -05:00
59313f3c90
daq1: ADC DMA must be in none-cyclic mode
2016-02-24 14:37:19 +02:00
c0a559a9b1
daq1: Fix some typos in the SPI wrapper
2016-02-24 14:31:56 +02:00
8ccd8d87bb
daq2: A10GX, increase analog/digital reset durations
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- reset the xcvr_rst_cntrl only from the axi_jesd_xcvr
- checked separate RX/TX reset per channel
2016-02-23 11:41:38 +02:00
89f7aadfb1
fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output
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This will allow for the transceivers to be reset by the axi_jesd_xcvr core
2016-02-23 11:31:07 +02:00
4fb6589b2d
pzsdr/ccfmc: add fan controls
2016-02-19 16:40:54 -05:00
377461e0d4
Merge branch 'hdl_2015_r2' into dev
2016-02-19 14:15:27 +02:00
0f37dd6424
fmcjesdadc1: Fixed project
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- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
ce760eb691
fmcadc2- add adf4355 access
2016-02-18 16:17:33 -05:00
a8e9d72273
adc/dac - prefix parameters
2016-02-17 14:16:04 -05:00
d94f157454
arradio: Changed ADC/DAC DMA address length to 24 bit
2016-02-16 15:27:51 +02:00
43e03ca6f7
arradio: Updated project
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- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
2016-02-16 14:50:23 +02:00
5518c47ca4
daq1_cpld: Set Input and tristate I/O termination mode to FLOAT
2016-02-15 19:27:59 +02:00
051ac307e6
daq1_cpld: Do not forward the first eight clock cycles of fmc_spi_sclk to sclk
2016-02-15 19:26:58 +02:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
Lars-Peter Clausen