zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
1,401 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

16 Commits (7d2239986081613432eb56742509efd7d551d080)

Author SHA1 Message Date
Lars-Peter Clausen b6458f9aab axi_dmac: Move axi_repack block to its own module 
Move the axi_repack block to its own module. This allows it to use it
outside of the DMA controller.

Also rename it to util_axis_resize to better reflect its function.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-04-08 15:55:17 +02:00
Lars-Peter Clausen 6ba0667939 axi_dmac: Add fifo_wr/fifo_rd interfaces 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-04-08 13:29:25 +02:00
Lars-Peter Clausen d17cd22ef1 adi_ip.tcl: Allow to directly specify the vlnv string for adi_add_bus() 
Modify the adi_add_bus() function to take the full vlnv strings instead of just the bus type.

This makes the function more flexible and e.g. allows to handle buses from other vendors.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-04-08 13:29:25 +02:00
Rejeesh Kutty 7224ca1f0c dma: moved 2015-04-07 15:35:47 -04:00
Istvan Csomortani 96899313d8 axi_dmac: Fix constraint 
Change the constraint file extension to .xdc, no more need for the .tcl workaround.
 2015-01-23 18:51:25 +02:00
Adrian Costina 121a416916 axi_dmac: Fixed constraints for axi_dmac core 2014-10-22 13:07:55 +03:00
Lars-Peter Clausen 22169c4a9c axi_dmac: Add default driver values for optional input ports 
This silences warnings from the tools about undriven ports.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-10-10 16:25:46 +03:00
Lars-Peter Clausen e7dbdff60c axi_dmac: Hide fifo_wr_sync signal if C_SYNC_TRANSFER_START != 1 
The fifo_wr_sync signal is only used when C_SYNC_TRANSFER_START = 1, so hide it otherwise.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-10-10 16:25:41 +03:00
Lars-Peter Clausen 8557073b56 axi_dmac: Hide fifo_wr bus when source type is not the fifo interface 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-10-10 16:25:33 +03:00
Lars-Peter Clausen 3e6f553ce3 axi_dmac: Add clock signal spec for m_axis/s_axis bus 
This silences warnings from the tools about having no clock assigned to the bus.
Also fix the name of the TVALID signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-10-10 16:25:24 +03:00
Rejeesh Kutty 88a3b7f8fd library: remove all constraints for now 2014-10-07 16:59:19 -04:00
Lars-Peter Clausen c927e90ee1 axi_dmac/axi_fifo: Add missing file 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-09-15 21:04:57 +02:00
Rejeesh Kutty 1396a215e5 library: local constraints 2014-08-14 15:09:47 -04:00
Rejeesh Kutty 56ddce1e8c dmac: create fifo interface to avoid being treated as axi control stream 2014-05-27 10:25:14 -04:00
Lars-Peter Clausen f02ba999ae axi_dmac: Add support for DMA bus widths other than 64 bit 
There were a few place in the core where it assumed a 64-bit wide bus. Make this
configurable using parameters. The patch also adds support for having different
DMA bus widths on the source and destination side.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-13 13:20:10 +01:00
Adrian Costina 831c19ea84 Added axi_dmac, axi_fifo and misc files in library 2014-03-06 18:16:02 +02:00